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Commit 5fd92657 authored by Prasad Sodagudi's avatar Prasad Sodagudi
Browse files

ARM: dts: msm: Change blsp1_uart0 address for msmtitanium



Update the blsp1_uart0 address for console support
in msmtitanium SoC.

Change-Id: I3ad97b02a7b3476b5e288b078bac9e7007a0987d
Signed-off-by: default avatarPrasad Sodagudi <psodagud@codeaurora.org>
parent 25cdb235
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+1 −1
Original line number Diff line number Diff line
@@ -16,7 +16,7 @@
&soc {
};

&blsp1_uart2 {
&blsp1_uart0 {
	status = "ok";
	pinctrl-names = "default";
	pinctrl-0 = <&uart_console_active>;
+1 −1
Original line number Diff line number Diff line
@@ -16,7 +16,7 @@
&soc {
};

&blsp1_uart2 {
&blsp1_uart0 {
	status = "ok";
	pinctrl-names = "default";
	pinctrl-0 = <&uart_console_active>;
+1 −1
Original line number Diff line number Diff line
@@ -27,7 +27,7 @@
	};
};

&blsp1_uart2 {
&blsp1_uart0 {
	status = "ok";
	pinctrl-names = "default";
	pinctrl-0 = <&uart_console_active>;
+1 −1
Original line number Diff line number Diff line
@@ -23,7 +23,7 @@
	qcom,board-id= <16 0>;
};

&blsp1_uart2 {
&blsp1_uart0 {
	status = "ok";
	pinctrl-names = "default";
	pinctrl-0 = <&uart_console_sleep>;
+4 −4
Original line number Diff line number Diff line
@@ -456,12 +456,12 @@
		};
	};

	blsp1_uart2: serial@78b0000 {
	blsp1_uart0: serial@78af000 {
		compatible = "qcom,msm-lsuart-v14";
		reg = <0x78b0000 0x200>;
		interrupts = <0 108 0>;
		reg = <0x78af000 0x200>;
		interrupts = <0 107 0>;
		status = "disabled";
		clocks = <&clock_gcc clk_gcc_blsp1_uart2_apps_clk>,
		clocks = <&clock_gcc clk_gcc_blsp1_uart1_apps_clk>,
		<&clock_gcc clk_gcc_blsp1_ahb_clk>;
		clock-names = "core_clk", "iface_clk";
	};