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Commit 394c8132 authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "msm: kgsl: For a5xx set GPU in privileged mode during self programming"

parents 926233dc 01d1594b

drivers/gpu/msm/a5xx_reg.h

+1 −0
Original line number Diff line number Diff line
@@ -85,6 +85,7 @@ 
#define A5XX_CP_PFP_UCODE_DBG_DATA       0x82B

#define A5XX_CP_ME_UCODE_DBG_ADDR        0x82F

#define A5XX_CP_ME_UCODE_DBG_DATA        0x830

#define A5XX_CP_CNTL                     0x831

#define A5XX_CP_ME_CNTL                  0x832

#define A5XX_CP_CHICKEN_DBG              0x833

#define A5XX_CP_PFP_INSTR_BASE_LO        0x835

drivers/gpu/msm/adreno-gpulist.h

+26 −0
Original line number Diff line number Diff line
@@ -185,6 +185,32 @@ static const struct adreno_gpu_core adreno_gpulist[] = { 
		.max_power = 5448,

		.regfw_name = "a530v3_seq.fw2",

	},

	{

		.gpurev = ADRENO_REV_A505,

		.core = 5,

		.major = 0,

		.minor = 5,

		.patchid = ANY_ID,

		.pm4fw_name = "a530_pm4.fw",

		.pfpfw_name = "a530_pfp.fw",

		.gpudev = &adreno_a5xx_gpudev,

		.gmem_size = (SZ_128K + SZ_8K),

		.num_protected_regs = 0x20,

		.busy_mask = 0xFFFFFFFE,

	},

	{

		.gpurev = ADRENO_REV_A506,

		.core = 5,

		.major = 0,

		.minor = 6,

		.patchid = ANY_ID,

		.pm4fw_name = "a530_pm4.fw",

		.pfpfw_name = "a530_pfp.fw",

		.gpudev = &adreno_a5xx_gpudev,

		.gmem_size = (SZ_128K + SZ_8K),

		.num_protected_regs = 0x20,

		.busy_mask = 0xFFFFFFFE,

	},

	{

		.gpurev = ADRENO_REV_A510,

		.core = 5,

drivers/gpu/msm/adreno.h

+9 −0
Original line number Diff line number Diff line
@@ -152,6 +152,8 @@ enum adreno_gpurev { 
	ADRENO_REV_A418 = 418,

	ADRENO_REV_A420 = 420,

	ADRENO_REV_A430 = 430,

	ADRENO_REV_A505 = 505,

	ADRENO_REV_A506 = 506,

	ADRENO_REV_A510 = 510,

	ADRENO_REV_A530 = 530,

};
@@ -921,6 +923,8 @@ static inline int adreno_is_a5xx(struct adreno_device *adreno_dev) 
			ADRENO_GPUREV(adreno_dev) < 600;

}



ADRENO_TARGET(a505, ADRENO_REV_A505)

ADRENO_TARGET(a506, ADRENO_REV_A506)

ADRENO_TARGET(a510, ADRENO_REV_A510)

ADRENO_TARGET(a530, ADRENO_REV_A530)
@@ -942,6 +946,11 @@ static inline int adreno_is_a530v3(struct adreno_device *adreno_dev) 
		(ADRENO_CHIPID_PATCH(adreno_dev->chipid) == 2);

}



static inline int adreno_is_a505_or_a506(struct adreno_device *adreno_dev)

{

	return ADRENO_GPUREV(adreno_dev) >= 505 &&

			ADRENO_GPUREV(adreno_dev) <= 506;

}

/**

 * adreno_context_timestamp() - Return the last queued timestamp for the context

 * @k_ctxt: Pointer to the KGSL context to query

drivers/gpu/msm/adreno_a5xx.c

+67 −5
Original line number Diff line number Diff line
@@ -41,6 +41,8 @@ static const struct adreno_vbif_data a530_vbif[] = { 
static const struct adreno_vbif_platform a5xx_vbif_platforms[] = {

	{ adreno_is_a530, a530_vbif },

	{ adreno_is_a510, a530_vbif },

	{ adreno_is_a505, a530_vbif },

	{ adreno_is_a506, a530_vbif },

};



#define PREEMPT_RECORD(_field) \
@@ -218,7 +220,7 @@ static int a5xx_preemption_init(struct adreno_device *adreno_dev) 


	/* Allocate mem for storing preemption smmu record */

	return kgsl_allocate_global(device, &iommu->smmu_info, PAGE_SIZE,

		KGSL_MEMDESC_PRIVILEGED, 0);

		KGSL_MEMFLAGS_GPUREADONLY, KGSL_MEMDESC_PRIVILEGED);

}



/*
@@ -354,7 +356,15 @@ static void a5xx_gpudev_init(struct adreno_device *adreno_dev) 


	gpudev = ADRENO_GPU_DEVICE(adreno_dev);



	if (adreno_is_a510(adreno_dev)) {

	if (adreno_is_a505_or_a506(adreno_dev)) {

		gpudev->snapshot_data->sect_sizes->cp_meq = 32;

		gpudev->snapshot_data->sect_sizes->cp_merciu = 1024;

		gpudev->snapshot_data->sect_sizes->roq = 256;



		/* A505 & A506 having 3 XIN ports in VBIF */

		gpudev->vbif_xin_halt_ctrl0_mask =

				A510_VBIF_XIN_HALT_CTRL0_MASK;

	} else if (adreno_is_a510(adreno_dev)) {

		gpudev->snapshot_data->sect_sizes->cp_meq = 32;

		gpudev->snapshot_data->sect_sizes->cp_merciu = 32;

		gpudev->snapshot_data->sect_sizes->roq = 256;
@@ -966,6 +976,44 @@ struct kgsl_hwcg_reg { 
	unsigned int val;

};



static const struct kgsl_hwcg_reg a50x_hwcg_regs[] = {

	{A5XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},

	{A5XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},

	{A5XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF},

	{A5XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},

	{A5XX_RBBM_CLOCK_CNTL_TP0, 0x22222222},

	{A5XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},

	{A5XX_RBBM_CLOCK_CNTL3_TP0, 0x00002222},

	{A5XX_RBBM_CLOCK_HYST_TP0, 0x77777777},

	{A5XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},

	{A5XX_RBBM_CLOCK_HYST3_TP0, 0x00007777},

	{A5XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},

	{A5XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},

	{A5XX_RBBM_CLOCK_DELAY3_TP0, 0x00001111},

	{A5XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},

	{A5XX_RBBM_CLOCK_HYST_UCHE, 0x00444444},

	{A5XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},

	{A5XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},

	{A5XX_RBBM_CLOCK_CNTL2_RB0, 0x00222222},

	{A5XX_RBBM_CLOCK_CNTL_CCU0, 0x00022220},

	{A5XX_RBBM_CLOCK_CNTL_RAC, 0x05522222},

	{A5XX_RBBM_CLOCK_CNTL2_RAC, 0x00555555},

	{A5XX_RBBM_CLOCK_HYST_RB_CCU0, 0x04040404},

	{A5XX_RBBM_CLOCK_HYST_RAC, 0x07444044},

	{A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_0, 0x00000002},

	{A5XX_RBBM_CLOCK_DELAY_RAC, 0x00010011},

	{A5XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},

	{A5XX_RBBM_CLOCK_MODE_GPC, 0x02222222},

	{A5XX_RBBM_CLOCK_MODE_VFD, 0x00002222},

	{A5XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},

	{A5XX_RBBM_CLOCK_HYST_GPC, 0x04104004},

	{A5XX_RBBM_CLOCK_HYST_VFD, 0x00000000},

	{A5XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},

	{A5XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},

	{A5XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},

	{A5XX_RBBM_CLOCK_DELAY_VFD, 0x00002222}

};



static const struct kgsl_hwcg_reg a510_hwcg_regs[] = {

	{A5XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},

	{A5XX_RBBM_CLOCK_CNTL_SP1, 0x02222222},
@@ -1128,6 +1176,8 @@ static const struct { 
	{ adreno_is_a530v3, a530_hwcg_regs, ARRAY_SIZE(a530_hwcg_regs) },

	{ adreno_is_a530v2, a530_hwcg_regs, ARRAY_SIZE(a530_hwcg_regs) },

	{ adreno_is_a510, a510_hwcg_regs, ARRAY_SIZE(a510_hwcg_regs) },

	{ adreno_is_a505, a50x_hwcg_regs, ARRAY_SIZE(a50x_hwcg_regs) },

	{ adreno_is_a506, a50x_hwcg_regs, ARRAY_SIZE(a50x_hwcg_regs) },

};



static void a5xx_hwcg_init(struct adreno_device *adreno_dev)
@@ -1233,6 +1283,9 @@ static void _load_regfile(struct adreno_device *adreno_dev) 
	uint32_t *block;

	int ret = -EINVAL;



	if (!adreno_dev->gpucore->regfw_name)

		return;



	ret = request_firmware(&fw, adreno_dev->gpucore->regfw_name,

			device->dev);

	if (ret) {
@@ -1720,7 +1773,12 @@ static void a5xx_start(struct adreno_device *adreno_dev) 
	 * Below CP registers are 0x0 by default, program init

	 * values based on a5xx flavor.

	 */

	if (adreno_is_a510(adreno_dev)) {

	if (adreno_is_a505_or_a506(adreno_dev)) {

		kgsl_regwrite(device, A5XX_CP_MEQ_THRESHOLDS, 0x20);

		kgsl_regwrite(device, A5XX_CP_MERCIU_SIZE, 0x400);

		kgsl_regwrite(device, A5XX_CP_ROQ_THRESHOLDS_2, 0x40000030);

		kgsl_regwrite(device, A5XX_CP_ROQ_THRESHOLDS_1, 0x20100D0A);

	} else if (adreno_is_a510(adreno_dev)) {

		kgsl_regwrite(device, A5XX_CP_MEQ_THRESHOLDS, 0x20);

		kgsl_regwrite(device, A5XX_CP_MERCIU_SIZE, 0x20);

		kgsl_regwrite(device, A5XX_CP_ROQ_THRESHOLDS_2, 0x40000030);
@@ -1734,9 +1792,12 @@ static void a5xx_start(struct adreno_device *adreno_dev) 


	/*

	 * vtxFifo and primFifo thresholds default values

	 * are different for A510.

	 * are different.

	 */

	if (adreno_is_a510(adreno_dev))

	if (adreno_is_a505_or_a506(adreno_dev))

		kgsl_regwrite(device, A5XX_PC_DBG_ECO_CNTL,

						(0x100 << 11 | 0x100 << 22));

	else if (adreno_is_a510(adreno_dev))

		kgsl_regwrite(device, A5XX_PC_DBG_ECO_CNTL,

						(0x200 << 11 | 0x200 << 22));

	else
@@ -2578,6 +2639,7 @@ static unsigned int a5xx_register_offsets[ADRENO_REG_REGISTER_MAX] = { 
	ADRENO_REG_DEFINE(ADRENO_REG_CP_RB_BASE_HI, A5XX_CP_RB_BASE_HI),

	ADRENO_REG_DEFINE(ADRENO_REG_CP_RB_RPTR, A5XX_CP_RB_RPTR),

	ADRENO_REG_DEFINE(ADRENO_REG_CP_RB_WPTR, A5XX_CP_RB_WPTR),

	ADRENO_REG_DEFINE(ADRENO_REG_CP_CNTL, A5XX_CP_CNTL),

	ADRENO_REG_DEFINE(ADRENO_REG_CP_ME_CNTL, A5XX_CP_ME_CNTL),

	ADRENO_REG_DEFINE(ADRENO_REG_CP_RB_CNTL, A5XX_CP_RB_CNTL),

	ADRENO_REG_DEFINE(ADRENO_REG_CP_IB1_BASE, A5XX_CP_IB1_BASE),

drivers/gpu/msm/adreno_iommu.c

+12 −11
Original line number Diff line number Diff line
@@ -298,6 +298,10 @@ unsigned int adreno_iommu_set_apriv(struct adreno_device *adreno_dev, 
{

	unsigned int *cmds_orig = cmds;



	/* adreno 3xx doesn't have the CP_CNTL.APRIV field */

	if (adreno_is_a3xx(adreno_dev))

		return 0;



	cmds += cp_wait_for_idle(adreno_dev, cmds);

	cmds += cp_wait_for_me(adreno_dev, cmds);

	*cmds++ = cp_register(adreno_dev, adreno_getreg(adreno_dev,
@@ -590,13 +594,11 @@ unsigned int adreno_iommu_set_pt_generate_cmds( 
	unsigned int *cmds_orig = cmds;

	struct kgsl_iommu *iommu = adreno_dev->dev.mmu.priv;



	/* If we are in a fault the MMU will be reset soon */

	if (test_bit(ADRENO_DEVICE_FAULT, &adreno_dev->priv))

		return 0;



	ttbr0 = kgsl_mmu_pagetable_get_ttbr0(pt);

	contextidr = kgsl_mmu_pagetable_get_contextidr(pt);



	cmds += adreno_iommu_set_apriv(adreno_dev, cmds, 1);



	cmds += _adreno_iommu_add_idle_indirect_cmds(adreno_dev, cmds,

		device->mmu.setstate_memory.gpuaddr +

		KGSL_IOMMU_SETSTATE_NOP_OFFSET);
@@ -621,6 +623,8 @@ unsigned int adreno_iommu_set_pt_generate_cmds( 
	/* invalidate all base pointers */

	cmds += cp_invalidate_state(adreno_dev, cmds);



	cmds += adreno_iommu_set_apriv(adreno_dev, cmds, 0);



	return cmds - cmds_orig;

}
@@ -827,17 +831,14 @@ static int _set_pagetable_gpu(struct adreno_ringbuffer *rb, 


	cmds = link;



	kgsl_mmu_enable_clk(&device->mmu);

	/* If we are in a fault the MMU will be reset soon */

	if (test_bit(ADRENO_DEVICE_FAULT, &adreno_dev->priv))

		return 0;



	/* pt switch may use privileged memory */

	if (adreno_is_a4xx(adreno_dev))

		cmds += adreno_iommu_set_apriv(adreno_dev, cmds, 1);

	kgsl_mmu_enable_clk(&device->mmu);



	cmds += adreno_iommu_set_pt_generate_cmds(rb, cmds, new_pt);



	if (adreno_is_a4xx(adreno_dev))

		cmds += adreno_iommu_set_apriv(adreno_dev, cmds, 0);



	if ((unsigned int) (cmds - link) > (PAGE_SIZE / sizeof(unsigned int))) {

		KGSL_DRV_ERR(device, "Temp command buffer overflow\n");

		BUG();