Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 01d1594b authored by Sunil Khatri's avatar Sunil Khatri Committed by Jordan Crouse
Browse files

msm: kgsl: For a5xx set GPU in privileged mode during self programming 



In self programing path for accessing privileged memory
GPU needs to be in privileged mode. Setting GPU in
privileged mode before accessing such memory and
reset it later.

Change-Id: I4522965b73fed9fb6b9a33f3c555d2398a176d55
Signed-off-by: default avatarSunil Khatri <sunilkh@codeaurora.org>
Signed-off-by: default avatarJeremy Gebben <jgebben@codeaurora.org>
parent 2e4e3c2c

drivers/gpu/msm/a5xx_reg.h

+1 −0
Original line number Diff line number Diff line
@@ -85,6 +85,7 @@ 
#define A5XX_CP_PFP_UCODE_DBG_DATA       0x82B

#define A5XX_CP_ME_UCODE_DBG_ADDR        0x82F

#define A5XX_CP_ME_UCODE_DBG_DATA        0x830

#define A5XX_CP_CNTL                     0x831

#define A5XX_CP_ME_CNTL                  0x832

#define A5XX_CP_CHICKEN_DBG              0x833

#define A5XX_CP_PFP_INSTR_BASE_LO        0x835

drivers/gpu/msm/adreno_a5xx.c

+2 −1
Original line number Diff line number Diff line
@@ -220,7 +220,7 @@ static int a5xx_preemption_init(struct adreno_device *adreno_dev) 


	/* Allocate mem for storing preemption smmu record */

	return kgsl_allocate_global(device, &iommu->smmu_info, PAGE_SIZE,

		KGSL_MEMDESC_PRIVILEGED, 0);

		KGSL_MEMFLAGS_GPUREADONLY, KGSL_MEMDESC_PRIVILEGED);

}



/*
@@ -2639,6 +2639,7 @@ static unsigned int a5xx_register_offsets[ADRENO_REG_REGISTER_MAX] = { 
	ADRENO_REG_DEFINE(ADRENO_REG_CP_RB_BASE_HI, A5XX_CP_RB_BASE_HI),

	ADRENO_REG_DEFINE(ADRENO_REG_CP_RB_RPTR, A5XX_CP_RB_RPTR),

	ADRENO_REG_DEFINE(ADRENO_REG_CP_RB_WPTR, A5XX_CP_RB_WPTR),

	ADRENO_REG_DEFINE(ADRENO_REG_CP_CNTL, A5XX_CP_CNTL),

	ADRENO_REG_DEFINE(ADRENO_REG_CP_ME_CNTL, A5XX_CP_ME_CNTL),

	ADRENO_REG_DEFINE(ADRENO_REG_CP_RB_CNTL, A5XX_CP_RB_CNTL),

	ADRENO_REG_DEFINE(ADRENO_REG_CP_IB1_BASE, A5XX_CP_IB1_BASE),

drivers/gpu/msm/adreno_iommu.c

+12 −11
Original line number Diff line number Diff line
@@ -298,6 +298,10 @@ unsigned int adreno_iommu_set_apriv(struct adreno_device *adreno_dev, 
{

	unsigned int *cmds_orig = cmds;



	/* adreno 3xx doesn't have the CP_CNTL.APRIV field */

	if (adreno_is_a3xx(adreno_dev))

		return 0;



	cmds += cp_wait_for_idle(adreno_dev, cmds);

	cmds += cp_wait_for_me(adreno_dev, cmds);

	*cmds++ = cp_register(adreno_dev, adreno_getreg(adreno_dev,
@@ -590,13 +594,11 @@ unsigned int adreno_iommu_set_pt_generate_cmds( 
	unsigned int *cmds_orig = cmds;

	struct kgsl_iommu *iommu = adreno_dev->dev.mmu.priv;



	/* If we are in a fault the MMU will be reset soon */

	if (test_bit(ADRENO_DEVICE_FAULT, &adreno_dev->priv))

		return 0;



	ttbr0 = kgsl_mmu_pagetable_get_ttbr0(pt);

	contextidr = kgsl_mmu_pagetable_get_contextidr(pt);



	cmds += adreno_iommu_set_apriv(adreno_dev, cmds, 1);



	cmds += _adreno_iommu_add_idle_indirect_cmds(adreno_dev, cmds,

		device->mmu.setstate_memory.gpuaddr +

		KGSL_IOMMU_SETSTATE_NOP_OFFSET);
@@ -621,6 +623,8 @@ unsigned int adreno_iommu_set_pt_generate_cmds( 
	/* invalidate all base pointers */

	cmds += cp_invalidate_state(adreno_dev, cmds);



	cmds += adreno_iommu_set_apriv(adreno_dev, cmds, 0);



	return cmds - cmds_orig;

}
@@ -827,17 +831,14 @@ static int _set_pagetable_gpu(struct adreno_ringbuffer *rb, 


	cmds = link;



	kgsl_mmu_enable_clk(&device->mmu);

	/* If we are in a fault the MMU will be reset soon */

	if (test_bit(ADRENO_DEVICE_FAULT, &adreno_dev->priv))

		return 0;



	/* pt switch may use privileged memory */

	if (adreno_is_a4xx(adreno_dev))

		cmds += adreno_iommu_set_apriv(adreno_dev, cmds, 1);

	kgsl_mmu_enable_clk(&device->mmu);



	cmds += adreno_iommu_set_pt_generate_cmds(rb, cmds, new_pt);



	if (adreno_is_a4xx(adreno_dev))

		cmds += adreno_iommu_set_apriv(adreno_dev, cmds, 0);



	if ((unsigned int) (cmds - link) > (PAGE_SIZE / sizeof(unsigned int))) {

		KGSL_DRV_ERR(device, "Temp command buffer overflow\n");

		BUG();

drivers/gpu/msm/adreno_ringbuffer.c

+3 −29
Original line number Diff line number Diff line
@@ -1248,31 +1248,6 @@ int adreno_ringbuffer_waittimestamp(struct adreno_ringbuffer *rb, 
	return ret;

}



/**

 * adreno_ringbuffer_pt_switch_cmds() - Add commands to switch the pagetable

 * @rb: The ringbuffer on which the commands are going to be submitted

 * @cmds: The pointer where the commands are copied

 *

 * Returns the number of DWORDS added to cmds pointer

 */

static int

adreno_ringbuffer_pt_switch_cmds(struct adreno_ringbuffer *rb,

				unsigned int *cmds,

				struct kgsl_pagetable *pt)

{

	unsigned int *cmds_orig = cmds;

	struct adreno_device *adreno_dev = ADRENO_DEVICE(rb->device);



	cmds += adreno_iommu_set_apriv(adreno_dev, cmds, 1);



	cmds += adreno_iommu_set_pt_generate_cmds(rb, cmds, pt);



	cmds += adreno_iommu_set_apriv(adreno_dev, cmds, 0);



	return cmds - cmds_orig;

}





/**

 * adreno_ringbuffer_submit_preempt_token() - Submit a preempt token

 * @rb: Ringbuffer in which the token is submitted
@@ -1320,12 +1295,11 @@ int adreno_ringbuffer_submit_preempt_token(struct adreno_ringbuffer *rb, 
			 */

			BUG_ON(!pt);

			/* set the ringbuffer for incoming RB */

			pt_switch_sizedwords = adreno_ringbuffer_pt_switch_cmds(

								incoming_rb,

			pt_switch_sizedwords =

				adreno_iommu_set_pt_generate_cmds(incoming_rb,

								&link[0], pt);

			total_sizedwords += pt_switch_sizedwords;



			total_sizedwords = total_sizedwords +

						pt_switch_sizedwords;

		}

	}