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Commit 315bd300 authored by Harshdeep Dhatt's avatar Harshdeep Dhatt Committed by Gerrit - the friendly Code Review server
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msm: kgsl: Zero out the top 32 bits of alwayson reads 



The top 32 bits of alwayson when read through CPU can
sometimes be incorrect because of hardware race condition between
CP and CPU. Therefore, zero out the top 32 bits before returning
to user.

CRs-Fixed: 864922
Change-Id: I8c0addce5627168d15ce43218cd26195a4f40c6b
Signed-off-by: default avatarHarshdeep Dhatt <hdhatt@codeaurora.org>
parent 65bdd3d2

drivers/gpu/msm/adreno.c

+6 −1
Original line number Diff line number Diff line
@@ -1233,9 +1233,14 @@ static int adreno_init(struct kgsl_device *device) 


		adreno_dev->cmdbatch_profile_index = 0;



		if (r == 0)

		if (r == 0) {

			set_bit(ADRENO_DEVICE_CMDBATCH_PROFILE,

				&adreno_dev->priv);

			kgsl_sharedmem_set(&adreno_dev->dev,

				&adreno_dev->cmdbatch_profile_buffer, 0, 0,

				PAGE_SIZE);

		}



	}



	if (ADRENO_FEATURE(adreno_dev, ADRENO_PREEMPTION)) {

drivers/gpu/msm/adreno_ringbuffer.c

+24 −3
Original line number Diff line number Diff line
@@ -94,11 +94,20 @@ void adreno_ringbuffer_submit(struct adreno_ringbuffer *rb, 
		local_irq_save(flags);



		/* Read always on registers */

		if (!adreno_is_a3xx(adreno_dev))

		if (!adreno_is_a3xx(adreno_dev)) {

			adreno_readreg64(adreno_dev,

				ADRENO_REG_RBBM_ALWAYSON_COUNTER_LO,

				ADRENO_REG_RBBM_ALWAYSON_COUNTER_HI,

				&time->ticks);



			/*

			 * Mask hi bits as they may be incorrect on

			 * a4x and some a5x

			 */

			if (ADRENO_GPUREV(adreno_dev) >= 400 &&

				ADRENO_GPUREV(adreno_dev) <= ADRENO_REV_A530)

				time->ticks &= 0xFFFFFFFF;

		}

		else

			time->ticks = 0;
@@ -874,7 +883,19 @@ static inline int _get_alwayson_counter(struct adreno_device *adreno_dev, 
	unsigned int *p = cmds;



	*p++ = cp_mem_packet(adreno_dev, CP_REG_TO_MEM, 2, 1);

	*p++ = adreno_getreg(adreno_dev, ADRENO_REG_RBBM_ALWAYSON_COUNTER_LO) |



	/*

	 * For a4x and some a5x the alwayson_hi read through CPU

	 * will be masked. Only do 32 bit CP reads for keeping the

	 * numbers consistent

	 */

	if (ADRENO_GPUREV(adreno_dev) >= 400 &&

		ADRENO_GPUREV(adreno_dev) <= ADRENO_REV_A530)

		*p++ = adreno_getreg(adreno_dev,

			ADRENO_REG_RBBM_ALWAYSON_COUNTER_LO);

	else

		*p++ = adreno_getreg(adreno_dev,

			ADRENO_REG_RBBM_ALWAYSON_COUNTER_LO) |

			(1 << 30) | (2 << 18);

	p += cp_gpuaddr(adreno_dev, p, gpuaddr);