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Commit 2f5aaa3d authored by Joseph Lo's avatar Joseph Lo Committed by Stephen Warren
Browse files

ARM: tegra: set up the correct L2 data RAM latency for Cortex-A15 



When there is a cluster power down cycle in suspend, we need to set up
the correct L2 RAM data RAM latency to make L2 cache work correctly. This
is only needed for cluster 0 and needs to be done in tegra_resume before
the cache is enabled.

Signed-off-by: default avatarJoseph Lo <josephl@nvidia.com>
Signed-off-by: default avatarStephen Warren <swarren@nvidia.com>
parent ac2527bf

arch/arm/mach-tegra/reset-handler.S

+1 −0
Original line number Diff line number Diff line
@@ -45,6 +45,7 @@ 
ENTRY(tegra_resume)

	check_cpu_part_num 0xc09, r8, r9

	bleq	v7_invalidate_l1

	blne	tegra_init_l2_for_a15



	cpu_id	r0

	tegra_get_soc_id TEGRA_APB_MISC_BASE, r6

arch/arm/mach-tegra/sleep.S

+22 −0
Original line number Diff line number Diff line
@@ -68,6 +68,28 @@ ENDPROC(tegra_disable_clean_inv_dcache) 
#endif



#ifdef CONFIG_PM_SLEEP

/*

 * tegra_init_l2_for_a15

 *

 * set up the correct L2 cache data RAM latency

 */

ENTRY(tegra_init_l2_for_a15)

	mrc	p15, 0, r0, c0, c0, 5

	ubfx	r0, r0, #8, #4

	tst	r0, #1				@ only need for cluster 0

	bne	_exit_init_l2_a15



	mrc	p15, 0x1, r0, c9, c0, 2

	and	r0, r0, #7

	cmp	r0, #2

	bicne	r0, r0, #7

	orrne	r0, r0, #2

	mcrne	p15, 0x1, r0, c9, c0, 2

_exit_init_l2_a15:



	mov	pc, lr

ENDPROC(tegra_init_l2_for_a15)



/*

 * tegra_sleep_cpu_finish(unsigned long v2p)

 *