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Commit ac2527bf authored by Joseph Lo's avatar Joseph Lo Committed by Stephen Warren
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ARM: tegra: add a flag for tegra_disable_clean_inv_dcache to do LoUIS or ALL 



Adding a flag for tegra_disable_clean_inv_dcache to flush cache as LoUIS
or ALL. After this patch, the v7_flush_dcache_louis is used for CPU hotplug
and CPU suspend in CPU power down (e.g. CPU idle power-down mode) case. And
the v7_flush_dcache_all is used for CPU cluster power down (e.g. suspend to
LP2 mode).

Signed-off-by: default avatarJoseph Lo <josephl@nvidia.com>
Signed-off-by: default avatarStephen Warren <swarren@nvidia.com>
parent c04c7754

arch/arm/mach-tegra/hotplug.c

+1 −1
Original line number Diff line number Diff line
@@ -37,7 +37,7 @@ int tegra_cpu_kill(unsigned cpu) 
void __ref tegra_cpu_die(unsigned int cpu)

{

	/* Clean L1 data cache */

	tegra_disable_clean_inv_dcache();

	tegra_disable_clean_inv_dcache(TEGRA_FLUSH_CACHE_LOUIS);



	/* Shut down the current CPU. */

	tegra_hotplug_shutdown();

arch/arm/mach-tegra/sleep-tegra20.S

+1 −0
Original line number Diff line number Diff line
@@ -191,6 +191,7 @@ ENTRY(tegra20_sleep_cpu_secondary_finish) 
	mrc	p15, 0, r11, c1, c0, 1  @ save actlr before exiting coherency



	/* Flush and disable the L1 data cache */

	mov	r0, #TEGRA_FLUSH_CACHE_LOUIS

	bl	tegra_disable_clean_inv_dcache



	mov32	r0, TEGRA_PMC_VIRT + PMC_SCRATCH41

arch/arm/mach-tegra/sleep-tegra30.S

+1 −0
Original line number Diff line number Diff line
@@ -137,6 +137,7 @@ ENTRY(tegra30_sleep_cpu_secondary_finish) 
	mov	r7, lr



	/* Flush and disable the L1 data cache */

	mov 	r0, #TEGRA_FLUSH_CACHE_LOUIS

	bl	tegra_disable_clean_inv_dcache



	/* Powergate this CPU. */

arch/arm/mach-tegra/sleep.S

+6 −1
Original line number Diff line number Diff line
@@ -56,7 +56,9 @@ ENTRY(tegra_disable_clean_inv_dcache) 
	isb



	/* Flush the D-cache */

	bl	v7_flush_dcache_louis

	cmp	r0, #TEGRA_FLUSH_CACHE_ALL

	blne	v7_flush_dcache_louis

	bleq	v7_flush_dcache_all



	/* Trun off coherency */

	exit_smp r4, r5
@@ -73,9 +75,12 @@ ENDPROC(tegra_disable_clean_inv_dcache) 
 * tegra?_tear_down_cpu

 */

ENTRY(tegra_sleep_cpu_finish)

	mov	r4, r0

	/* Flush and disable the L1 data cache */

	mov	r0, #TEGRA_FLUSH_CACHE_ALL

	bl	tegra_disable_clean_inv_dcache



	mov	r0, r4

	mov32	r6, tegra_tear_down_cpu

	ldr	r1, [r6]

	add	r1, r1, r0

arch/arm/mach-tegra/sleep.h

+5 −1
Original line number Diff line number Diff line
@@ -41,6 +41,10 @@ 
#define CPU_NOT_RESETTABLE	0

#endif



/* flag of tegra_disable_clean_inv_dcache to do LoUIS or all */

#define TEGRA_FLUSH_CACHE_LOUIS	0

#define TEGRA_FLUSH_CACHE_ALL	1



#ifdef __ASSEMBLY__

/* returns the offset of the flow controller halt register for a cpu */

.macro cpu_to_halt_reg rd, rcpu
@@ -144,7 +148,7 @@ void tegra_pen_lock(void); 
void tegra_pen_unlock(void);

void tegra_resume(void);

int tegra_sleep_cpu_finish(unsigned long);

void tegra_disable_clean_inv_dcache(void);

void tegra_disable_clean_inv_dcache(u32 flag);



#ifdef CONFIG_HOTPLUG_CPU

void tegra20_hotplug_shutdown(void);