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Commit 2b684c07 authored by Linus Torvalds's avatar Linus Torvalds
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Merge tag 'clk-for-linus-3.13' of git://git.linaro.org/people/mturquette/linux 

Pull clock framework changes from Mike Turquette:
 "The clock changes for 3.13 are an even mix of framework improvements &
  bug fixes along with updates to existing clock drivers and the
  additional of new clock drivers"

* tag 'clk-for-linus-3.13' of git://git.linaro.org/people/mturquette/linux:
  clk: new driver for efm32 SoC
  clk: of: helper for determining number of parent clocks
  clk/zynq: Fix possible memory leak
  clk: keystone: Build Keystone clock drivers
  clk: keystone: Add gate control clock driver
  clk: keystone: add Keystone PLL clock driver
  Documentation: Add documentation for APM X-Gene clock binding
  clk: arm64: Add DTS clock entry for APM X-Gene Storm SoC
  clk: Add APM X-Gene SoC clock driver
  clk: wm831x: get rid of the implementation of remove function
  clk: Correct lookup logic in clk_fetch_parent_index()
  clk: Use kcalloc() to allocate arrays
  clk: Add error handling to clk_fetch_parent_index()
parents c2d33069 9ed9c07d

Documentation/devicetree/bindings/clock/efm32-clock.txt

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* Clock bindings for Energy Micro efm32 Giant Gecko's Clock Management Unit



Required properties:

- compatible: Should be "efm32gg,cmu"

- reg: Base address and length of the register set

- interrupts: Interrupt used by the CMU

- #clock-cells: Should be <1>



The clock consumer should specify the desired clock by having the clock ID in

its "clocks" phandle cell. The header efm32-clk.h contains a list of available

IDs.

Documentation/devicetree/bindings/clock/keystone-gate.txt

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Status: Unstable - ABI compatibility may be broken in the future



Binding for Keystone gate control driver which uses PSC controller IP.



This binding uses the common clock binding[1].



[1] Documentation/devicetree/bindings/clock/clock-bindings.txt



Required properties:

- compatible : shall be "ti,keystone,psc-clock".

- #clock-cells : from common clock binding; shall be set to 0.

- clocks : parent clock phandle

- reg :	psc control and domain address address space

- reg-names : psc control and domain registers

- domain-id : psc domain id needed to check the transition state register



Optional properties:

- clock-output-names : From common clock binding to override the

			default output clock name

Example:

	clkusb: clkusb {

		#clock-cells = <0>;

		compatible = "ti,keystone,psc-clock";

		clocks = <&chipclk16>;

		clock-output-names = "usb";

		reg = <0x02350008 0xb00>, <0x02350000 0x400>;

		reg-names = "control", "domain";

		domain-id = <0>;

	};

Documentation/devicetree/bindings/clock/keystone-pll.txt

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Status: Unstable - ABI compatibility may be broken in the future



Binding for keystone PLLs. The main PLL IP typically has a multiplier,

a divider and a post divider. The additional PLL IPs like ARMPLL, DDRPLL

and PAPLL are controlled by the memory mapped register where as the Main

PLL is controlled by a PLL controller registers along with memory mapped

registers.



This binding uses the common clock binding[1].



[1] Documentation/devicetree/bindings/clock/clock-bindings.txt



Required properties:

- #clock-cells : from common clock binding; shall be set to 0.

- compatible : shall be "ti,keystone,main-pll-clock" or "ti,keystone,pll-clock"

- clocks : parent clock phandle

- reg - pll control0 and pll multipler registers

- reg-names : control and multiplier. The multiplier is applicable only for

		main pll clock

- fixed-postdiv : fixed post divider value



Example:

	mainpllclk: mainpllclk@2310110 {

		#clock-cells = <0>;

		compatible = "ti,keystone,main-pll-clock";

		clocks = <&refclkmain>;

		reg = <0x02620350 4>, <0x02310110 4>;

		reg-names = "control", "multiplier";

		fixed-postdiv = <2>;

	};



	papllclk: papllclk@2620358 {

		#clock-cells = <0>;

		compatible = "ti,keystone,pll-clock";

		clocks = <&refclkmain>;

		clock-output-names = "pa-pll-clk";

		reg = <0x02620358 4>;

		reg-names = "control";

		fixed-postdiv = <6>;

	};



Required properties:

- #clock-cells : from common clock binding; shall be set to 0.

- compatible : shall be "ti,keystone,pll-mux-clock"

- clocks : link phandles of parent clocks

- reg - pll mux register

- bit-shift : number of bits to shift the bit-mask

- bit-mask : arbitrary bitmask for programming the mux



Optional properties:

- clock-output-names : From common clock binding.



Example:

	mainmuxclk: mainmuxclk@2310108 {

		#clock-cells = <0>;

		compatible = "ti,keystone,pll-mux-clock";

		clocks = <&mainpllclk>, <&refclkmain>;

		reg = <0x02310108 4>;

		bit-shift = <23>;

		bit-mask = <1>;

		clock-output-names = "mainmuxclk";

	};



Required properties:

- #clock-cells : from common clock binding; shall be set to 0.

- compatible : shall be "ti,keystone,pll-divider-clock"

- clocks : parent clock phandle

- reg - pll mux register

- bit-shift : number of bits to shift the bit-mask

- bit-mask : arbitrary bitmask for programming the divider



Optional properties:

- clock-output-names : From common clock binding.



Example:

	gemtraceclk: gemtraceclk@2310120 {

		#clock-cells = <0>;

		compatible = "ti,keystone,pll-divider-clock";

		clocks = <&mainmuxclk>;

		reg = <0x02310120 4>;

		bit-shift = <0>;

		bit-mask = <8>;

		clock-output-names = "gemtraceclk";

	};

Documentation/devicetree/bindings/clock/xgene.txt

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Device Tree Clock bindings for APM X-Gene



This binding uses the common clock binding[1].



[1] Documentation/devicetree/bindings/clock/clock-bindings.txt



Required properties:

- compatible : shall be one of the following:

	"apm,xgene-socpll-clock" - for a X-Gene SoC PLL clock

	"apm,xgene-pcppll-clock" - for a X-Gene PCP PLL clock

	"apm,xgene-device-clock" - for a X-Gene device clock



Required properties for SoC or PCP PLL clocks:

- reg : shall be the physical PLL register address for the pll clock.

- clocks : shall be the input parent clock phandle for the clock. This should

	be the reference clock.

- #clock-cells : shall be set to 1.

- clock-output-names : shall be the name of the PLL referenced by derive

  clock.

Optional properties for PLL clocks:

- clock-names : shall be the name of the PLL. If missing, use the device name.



Required properties for device clocks:

- reg : shall be a list of address and length pairs describing the CSR

         reset and/or the divider. Either may be omitted, but at least

         one must be present.

 - reg-names : shall be a string list describing the reg resource. This

               may include "csr-reg" and/or "div-reg". If this property

               is not present, the reg property is assumed to describe

               only "csr-reg".

- clocks : shall be the input parent clock phandle for the clock.

- #clock-cells : shall be set to 1.

- clock-output-names : shall be the name of the device referenced.

Optional properties for device clocks:

- clock-names : shall be the name of the device clock. If missing, use the

                device name.

- csr-offset : Offset to the CSR reset register from the reset address base.

               Default is 0.

- csr-mask : CSR reset mask bit. Default is 0xF.

- enable-offset : Offset to the enable register from the reset address base.

                  Default is 0x8.

- enable-mask : CSR enable mask bit. Default is 0xF.

- divider-offset : Offset to the divider CSR register from the divider base.

                   Default is 0x0.

- divider-width : Width of the divider register. Default is 0.

- divider-shift : Bit shift of the divider register. Default is 0.



For example:



	pcppll: pcppll@17000100 {

		compatible = "apm,xgene-pcppll-clock";

		#clock-cells = <1>;

		clocks = <&refclk 0>;

		clock-names = "pcppll";

		reg = <0x0 0x17000100 0x0 0x1000>;

		clock-output-names = "pcppll";

		type = <0>;

	};



	socpll: socpll@17000120 {

		compatible = "apm,xgene-socpll-clock";

		#clock-cells = <1>;

		clocks = <&refclk 0>;

		clock-names = "socpll";

		reg = <0x0 0x17000120 0x0 0x1000>;

		clock-output-names = "socpll";

		type = <1>;

	};



	qmlclk: qmlclk {

		compatible = "apm,xgene-device-clock";

		#clock-cells = <1>;

		clocks = <&socplldiv2 0>;

		clock-names = "qmlclk";

		reg = <0x0 0x1703C000 0x0 0x1000>;

		reg-name = "csr-reg";

		clock-output-names = "qmlclk";

	};



	ethclk: ethclk {

		compatible = "apm,xgene-device-clock";

		#clock-cells = <1>;

		clocks = <&socplldiv2 0>;

		clock-names = "ethclk";

		reg = <0x0 0x17000000 0x0 0x1000>;

		reg-names = "div-reg";

		divider-offset = <0x238>;

		divider-width = <0x9>;

		divider-shift = <0x0>;

		clock-output-names = "ethclk";

	};



	apbclk: apbclk {

		compatible = "apm,xgene-device-clock";

		#clock-cells = <1>;

		clocks = <&ahbclk 0>;

		clock-names = "apbclk";

		reg = <0x0 0x1F2AC000 0x0 0x1000

			0x0 0x1F2AC000 0x0 0x1000>;

		reg-names = "csr-reg", "div-reg";

		csr-offset = <0x0>;

		csr-mask = <0x200>;

		enable-offset = <0x8>;

		enable-mask = <0x200>;

		divider-offset = <0x10>;

		divider-width = <0x2>;

		divider-shift = <0x0>;

		flags = <0x8>;

		clock-output-names = "apbclk";

	};

arch/arm64/boot/dts/apm-storm.dtsi

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@@ -103,6 +103,81 @@ 
		#size-cells = <2>;

		ranges;



		clocks {

			#address-cells = <2>;

			#size-cells = <2>;

			ranges;

			refclk: refclk {

				compatible = "fixed-clock";

				#clock-cells = <1>;

				clock-frequency = <100000000>;

				clock-output-names = "refclk";

			};



			pcppll: pcppll@17000100 {

				compatible = "apm,xgene-pcppll-clock";

				#clock-cells = <1>;

				clocks = <&refclk 0>;

				clock-names = "pcppll";

				reg = <0x0 0x17000100 0x0 0x1000>;

				clock-output-names = "pcppll";

				type = <0>;

			};



			socpll: socpll@17000120 {

				compatible = "apm,xgene-socpll-clock";

				#clock-cells = <1>;

				clocks = <&refclk 0>;

				clock-names = "socpll";

				reg = <0x0 0x17000120 0x0 0x1000>;

				clock-output-names = "socpll";

				type = <1>;

			};



			socplldiv2: socplldiv2  {

				compatible = "fixed-factor-clock";

				#clock-cells = <1>;

				clocks = <&socpll 0>;

				clock-names = "socplldiv2";

				clock-mult = <1>;

				clock-div = <2>;

				clock-output-names = "socplldiv2";

			};



			qmlclk: qmlclk {

				compatible = "apm,xgene-device-clock";

				#clock-cells = <1>;

				clocks = <&socplldiv2 0>;

				clock-names = "qmlclk";

				reg = <0x0 0x1703C000 0x0 0x1000>;

				reg-names = "csr-reg";

				clock-output-names = "qmlclk";

			};



			ethclk: ethclk {

				compatible = "apm,xgene-device-clock";

				#clock-cells = <1>;

				clocks = <&socplldiv2 0>;

				clock-names = "ethclk";

				reg = <0x0 0x17000000 0x0 0x1000>;

				reg-names = "div-reg";

				divider-offset = <0x238>;

				divider-width = <0x9>;

				divider-shift = <0x0>;

				clock-output-names = "ethclk";

			};



			eth8clk: eth8clk {

				compatible = "apm,xgene-device-clock";

				#clock-cells = <1>;

				clocks = <&ethclk 0>;

				clock-names = "eth8clk";

				reg = <0x0 0x1702C000 0x0 0x1000>;

				reg-names = "csr-reg";

				clock-output-names = "eth8clk";

			};

		};



		serial0: serial@1c020000 {

			device_type = "serial";

			compatible = "ns16550";