clk: msm: mdss: program correct divider for PLL configuration

In the current implementation dividers for PLL are getting
programmed in VCO set rate. During resolution switch use case
when we perform VCO set rate, we are programing the old divider
values where are new divider value get calculated after that
and never taking effect. Because of this display does not come
up sometimes. Fix this issue by programing the divider value as
soon as it gets calculated.

Change-Id: Icb26156727cd1684d837af0461dfb6c203848398
Signed-off-by: Sandeep Panda <spanda@codeaurora.org>