Loading Documentation/devicetree/bindings/media/video/msm-cpp.txt +2 −2 Original line number Diff line number Diff line Loading @@ -79,7 +79,7 @@ Example: camss-vdd-supply = <&gdsc_camss_top>; vdd-supply = <&gdsc_cpp>; clocks = <&clock_mmss clk_mmss_mmagic_ahb_clk>, <&clock_mmss clk_mmss_mmagic_axi_clk>, <&clock_gcc clk_mmssnoc_axi_clk>, <&clock_mmss clk_mmagic_camss_axi_clk>, <&clock_mmss clk_camss_top_ahb_clk>, <&clock_mmss clk_cpp_clk_src>, Loading @@ -90,7 +90,7 @@ Example: <&clock_mmss clk_camss_ahb_clk>; <&clock_mmss clk_smmu_cpp_axi_clk>, <&clock_mmss clk_camss_cpp_vbif_ahb_clk>, clock-names = "mmss_mmagic_ahb_clk", "mmss_mmagic_axi_clk", clock-names = "mmss_mmagic_ahb_clk", "mmssnoc_axi_clk", "mmagic_camss_axi_clk", "camss_top_ahb_clk", "cpp_core_clk", "camss_cpp_ahb_clk", "camss_cpp_axi_clk", "camss_cpp_clk", Loading Documentation/devicetree/bindings/media/video/msm-fd.txt +2 −2 Original line number Diff line number Diff line Loading @@ -59,7 +59,7 @@ Example: vdd-supply = <&gdsc_fd>; qcom,vdd-names = "mmagic-vdd", "camss-vdd", "vdd"; clocks = <&clock_mmss clk_mmss_mmagic_ahb_clk>, <&clock_mmss clk_mmss_mmagic_axi_clk>, <&clock_gcc clk_mmssnoc_axi_clk>, <&clock_mmss clk_mmagic_camss_axi_clk>, <&clock_mmss clk_camss_top_ahb_clk>, <&clock_mmss clk_fd_core_clk_src>, Loading @@ -71,7 +71,7 @@ Example: <&clock_mmss clk_camss_cpp_axi_clk>, <&clock_mmss clk_camss_cpp_vbif_ahb_clk>, <&clock_mmss clk_smmu_cpp_ahb_clk>; clock-names = "mmss_mmagic_ahb_clk", "mmss_mmagic_axi_clk" , clock-names = "mmss_mmagic_ahb_clk", "mmssnoc_axi_clk" , "mmagic_camss_axi_clk", "camss_top_ahb_clk", "fd_core_clk_src", "fd_core_clk", "fd_core_uar_clk", "fd_ahb_clk", Loading Documentation/devicetree/bindings/media/video/msm-jpeg.txt +6 −6 Original line number Diff line number Diff line Loading @@ -40,7 +40,7 @@ Example: qcom,vdd-names = "mmagic-vdd", "camss-vdd", "vdd"; clock-names = "core_clk", "iface_clk", "bus_clk0", "camss_top_ahb_clk", "camss_ahb_clk", "smmu_jpeg_axi_clk", "mmss_mmagic_ahb_clk", "mmss_mmagic_axi_clk", "mmss_mmagic_ahb_clk", "mmssnoc_axi_clk", "mmagic_camss_axi_clk"; clocks = <&clock_mmss clk_camss_jpeg0_clk>, <&clock_mmss clk_camss_jpeg_ahb_clk>, Loading @@ -49,7 +49,7 @@ Example: <&clock_mmss clk_camss_ahb_clk>, <&clock_mmss clk_smmu_jpeg_axi_clk>, <&clock_mmss clk_mmss_mmagic_ahb_clk>, <&clock_mmss clk_mmss_mmagic_axi_clk>, <&clock_gcc clk_mmssnoc_axi_clk>, <&clock_mmss clk_mmagic_camss_axi_clk>; qcom,clock-rates = <320000000 0 0 0 0 0 0 0 0>; qcom,vbif-reg-settings = <0x4 0x1>, Loading Loading @@ -78,7 +78,7 @@ Example: qcom,vdd-names = "mmagic-vdd", "camss-vdd", "vdd"; clock-names = "core_clk", "iface_clk", "bus_clk0", "camss_top_ahb_clk", "camss_ahb_clk", "smmu_jpeg_axi_clk", "mmss_mmagic_ahb_clk", "mmss_mmagic_axi_clk", "mmss_mmagic_ahb_clk", "mmssnoc_axi_clk", "mmagic_camss_axi_clk"; clocks = <&clock_mmss clk_camss_jpeg2_clk>, <&clock_mmss clk_camss_jpeg_ahb_clk>, Loading @@ -87,7 +87,7 @@ Example: <&clock_mmss clk_camss_ahb_clk>, <&clock_mmss clk_smmu_jpeg_axi_clk>, <&clock_mmss clk_mmss_mmagic_ahb_clk>, <&clock_mmss clk_mmss_mmagic_axi_clk>, <&clock_gcc clk_mmssnoc_axi_clk>, <&clock_mmss clk_mmagic_camss_axi_clk>; qcom,clock-rates = <266670000 0 0 0 0 0 0 0 0>; qcom,vbif-reg-settings = <0x4 0x1>, Loading Loading @@ -116,7 +116,7 @@ Example: qcom,vdd-names = "mmagic-vdd", "camss-vdd", "vdd"; clock-names = "core_clk", "iface_clk", "bus_clk0", "camss_top_ahb_clk", "camss_ahb_clk", "smmu_jpeg_axi_clk", "mmss_mmagic_ahb_clk", "mmss_mmagic_axi_clk", "mmss_mmagic_ahb_clk", "mmssnoc_axi_clk", "mmagic_camss_axi_clk"; clocks = <&clock_mmss clk_camss_jpeg_dma_clk>, <&clock_mmss clk_camss_jpeg_ahb_clk>, Loading @@ -125,7 +125,7 @@ Example: <&clock_mmss clk_camss_ahb_clk>, <&clock_mmss clk_smmu_jpeg_axi_clk>, <&clock_mmss clk_mmss_mmagic_ahb_clk>, <&clock_mmss clk_mmss_mmagic_axi_clk>, <&clock_gcc clk_mmssnoc_axi_clk>, <&clock_mmss clk_mmagic_camss_axi_clk>; qcom,clock-rates = <266670000 0 0 0 0 0 0 0 0>; qcom,vbif-reg-settings = <0x4 0x1>, Loading Documentation/devicetree/bindings/media/video/msm-jpegdma.txt +2 −2 Original line number Diff line number Diff line Loading @@ -41,7 +41,7 @@ Example: qcom,vdd-names = "mmagic-vdd", "camss-vdd", "vdd"; clock-names = "core_clk", "iface_clk", "bus_clk0", "camss_top_ahb_clk", "camss_ahb_clk", "smmu_jpeg_axi_clk", "mmss_mmagic_ahb_clk", "mmss_mmagic_axi_clk", "mmss_mmagic_ahb_clk", "mmssnoc_axi_clk", "mmagic_camss_axi_clk"; clocks = <&clock_mmss clk_camss_jpeg_dma_clk>, <&clock_mmss clk_camss_jpeg_ahb_clk>, Loading @@ -50,7 +50,7 @@ Example: <&clock_mmss clk_camss_ahb_clk>, <&clock_mmss clk_smmu_jpeg_axi_clk>, <&clock_mmss clk_mmss_mmagic_ahb_clk>, <&clock_mmss clk_mmss_mmagic_axi_clk>, <&clock_gcc clk_mmssnoc_axi_clk>, <&clock_mmss clk_mmagic_camss_axi_clk>; qcom,clock-rates = <266670000 0 0 0 0 0 0 0 0>, <400000000 0 0 0 0 0 0 0 0>; Loading arch/arm/boot/dts/qcom/msm-arm-smmu-8996v1.dtsi +12 −12 Original line number Diff line number Diff line Loading @@ -28,11 +28,11 @@ <&clock_mmss clk_mmss_mmagic_cfg_ahb_clk>, <&clock_mmss clk_smmu_jpeg_ahb_clk>, <&clock_mmss clk_smmu_jpeg_axi_clk>, <&clock_mmss clk_mmagic_bimc_axi_clk>, <&clock_gcc clk_mmssnoc_axi_clk>, <&clock_mmss clk_mmagic_camss_axi_clk>; clock-names = "mmagic_ahb_clk", "mmagic_cfg_ahb_clk", "jpeg_ahb_clk", "jpeg_axi_clk", "mmagic_bimc_axi_clk", "mmagic_camss_axi_clk"; "mmssnoc_axi_clk", "mmagic_camss_axi_clk"; #clock-cells = <1>; }; Loading Loading @@ -74,11 +74,11 @@ <&clock_mmss clk_mmss_mmagic_cfg_ahb_clk>, <&clock_mmss clk_smmu_vfe_ahb_clk>, <&clock_mmss clk_smmu_vfe_axi_clk>, <&clock_mmss clk_mmagic_bimc_axi_clk>, <&clock_gcc clk_mmssnoc_axi_clk>, <&clock_mmss clk_mmagic_camss_axi_clk>; clock-names = "mmagic_ahb_clk", "mmagic_cfg_ahb_clk", "vfe_ahb_clk", "vfe_axi_clk", "mmagic_bimc_axi_clk", "mmagic_camss_axi_clk"; "mmssnoc_axi_clk", "mmagic_camss_axi_clk"; #clock-cells = <1>; }; Loading @@ -99,11 +99,11 @@ <&clock_mmss clk_mmss_mmagic_cfg_ahb_clk>, <&clock_mmss clk_smmu_video_ahb_clk>, <&clock_mmss clk_smmu_video_axi_clk>, <&clock_mmss clk_mmagic_bimc_axi_clk>, <&clock_gcc clk_mmssnoc_axi_clk>, <&clock_mmss clk_mmagic_video_axi_clk>; clock-names = "mmagic_ahb_clk", "mmagic_cfg_ahb_clk", "video_ahb_clk", "video_axi_clk", "mmagic_bimc_axi_clk", "mmagic_video_axi_clk"; "mmssnoc_axi_clk", "mmagic_video_axi_clk"; #clock-cells = <1>; }; Loading @@ -124,11 +124,11 @@ <&clock_mmss clk_mmss_mmagic_cfg_ahb_clk>, <&clock_mmss clk_smmu_mdp_ahb_clk>, <&clock_mmss clk_smmu_mdp_axi_clk>, <&clock_mmss clk_mmagic_bimc_axi_clk>, <&clock_gcc clk_mmssnoc_axi_clk>, <&clock_mmss clk_mmagic_mdss_axi_clk>; clock-names = "mmagic_ahb_clk", "mmagic_cfg_ahb_clk", "mdp_ahb_clk", "mdp_axi_clk", "mmagic_bimc_axi_clk", "mmagic_mdss_axi_clk"; "mmssnoc_axi_clk", "mmagic_mdss_axi_clk"; #clock-cells = <1>; }; Loading @@ -147,11 +147,11 @@ <&clock_mmss clk_mmss_mmagic_cfg_ahb_clk>, <&clock_mmss clk_smmu_rot_ahb_clk>, <&clock_mmss clk_smmu_rot_axi_clk>, <&clock_mmss clk_mmagic_bimc_axi_clk>, <&clock_gcc clk_mmssnoc_axi_clk>, <&clock_mmss clk_mmagic_mdss_axi_clk>; clock-names = "mmagic_ahb_clk", "mmagic_cfg_ahb_clk", "rot_ahb_clk", "rot_axi_clk", "mmagic_bimc_axi_clk", "mmagic_mdss_axi_clk"; "mmssnoc_axi_clk", "mmagic_mdss_axi_clk"; #clock-cells = <1>; }; Loading @@ -171,11 +171,11 @@ <&clock_mmss clk_mmss_mmagic_cfg_ahb_clk>, <&clock_mmss clk_smmu_cpp_ahb_clk>, <&clock_mmss clk_smmu_cpp_axi_clk>, <&clock_mmss clk_mmagic_bimc_axi_clk>, <&clock_gcc clk_mmssnoc_axi_clk>, <&clock_mmss clk_mmagic_camss_axi_clk>; clock-names = "mmagic_ahb_clk", "mmagic_cfg_ahb_clk", "cpp_ahb_clk", "cpp_axi_clk", "mmagic_bimc_axi_clk", "mmagic_camss_axi_clk"; "mmssnoc_axi_clk", "mmagic_camss_axi_clk"; #clock-cells = <1>; }; Loading Loading
Documentation/devicetree/bindings/media/video/msm-cpp.txt +2 −2 Original line number Diff line number Diff line Loading @@ -79,7 +79,7 @@ Example: camss-vdd-supply = <&gdsc_camss_top>; vdd-supply = <&gdsc_cpp>; clocks = <&clock_mmss clk_mmss_mmagic_ahb_clk>, <&clock_mmss clk_mmss_mmagic_axi_clk>, <&clock_gcc clk_mmssnoc_axi_clk>, <&clock_mmss clk_mmagic_camss_axi_clk>, <&clock_mmss clk_camss_top_ahb_clk>, <&clock_mmss clk_cpp_clk_src>, Loading @@ -90,7 +90,7 @@ Example: <&clock_mmss clk_camss_ahb_clk>; <&clock_mmss clk_smmu_cpp_axi_clk>, <&clock_mmss clk_camss_cpp_vbif_ahb_clk>, clock-names = "mmss_mmagic_ahb_clk", "mmss_mmagic_axi_clk", clock-names = "mmss_mmagic_ahb_clk", "mmssnoc_axi_clk", "mmagic_camss_axi_clk", "camss_top_ahb_clk", "cpp_core_clk", "camss_cpp_ahb_clk", "camss_cpp_axi_clk", "camss_cpp_clk", Loading
Documentation/devicetree/bindings/media/video/msm-fd.txt +2 −2 Original line number Diff line number Diff line Loading @@ -59,7 +59,7 @@ Example: vdd-supply = <&gdsc_fd>; qcom,vdd-names = "mmagic-vdd", "camss-vdd", "vdd"; clocks = <&clock_mmss clk_mmss_mmagic_ahb_clk>, <&clock_mmss clk_mmss_mmagic_axi_clk>, <&clock_gcc clk_mmssnoc_axi_clk>, <&clock_mmss clk_mmagic_camss_axi_clk>, <&clock_mmss clk_camss_top_ahb_clk>, <&clock_mmss clk_fd_core_clk_src>, Loading @@ -71,7 +71,7 @@ Example: <&clock_mmss clk_camss_cpp_axi_clk>, <&clock_mmss clk_camss_cpp_vbif_ahb_clk>, <&clock_mmss clk_smmu_cpp_ahb_clk>; clock-names = "mmss_mmagic_ahb_clk", "mmss_mmagic_axi_clk" , clock-names = "mmss_mmagic_ahb_clk", "mmssnoc_axi_clk" , "mmagic_camss_axi_clk", "camss_top_ahb_clk", "fd_core_clk_src", "fd_core_clk", "fd_core_uar_clk", "fd_ahb_clk", Loading
Documentation/devicetree/bindings/media/video/msm-jpeg.txt +6 −6 Original line number Diff line number Diff line Loading @@ -40,7 +40,7 @@ Example: qcom,vdd-names = "mmagic-vdd", "camss-vdd", "vdd"; clock-names = "core_clk", "iface_clk", "bus_clk0", "camss_top_ahb_clk", "camss_ahb_clk", "smmu_jpeg_axi_clk", "mmss_mmagic_ahb_clk", "mmss_mmagic_axi_clk", "mmss_mmagic_ahb_clk", "mmssnoc_axi_clk", "mmagic_camss_axi_clk"; clocks = <&clock_mmss clk_camss_jpeg0_clk>, <&clock_mmss clk_camss_jpeg_ahb_clk>, Loading @@ -49,7 +49,7 @@ Example: <&clock_mmss clk_camss_ahb_clk>, <&clock_mmss clk_smmu_jpeg_axi_clk>, <&clock_mmss clk_mmss_mmagic_ahb_clk>, <&clock_mmss clk_mmss_mmagic_axi_clk>, <&clock_gcc clk_mmssnoc_axi_clk>, <&clock_mmss clk_mmagic_camss_axi_clk>; qcom,clock-rates = <320000000 0 0 0 0 0 0 0 0>; qcom,vbif-reg-settings = <0x4 0x1>, Loading Loading @@ -78,7 +78,7 @@ Example: qcom,vdd-names = "mmagic-vdd", "camss-vdd", "vdd"; clock-names = "core_clk", "iface_clk", "bus_clk0", "camss_top_ahb_clk", "camss_ahb_clk", "smmu_jpeg_axi_clk", "mmss_mmagic_ahb_clk", "mmss_mmagic_axi_clk", "mmss_mmagic_ahb_clk", "mmssnoc_axi_clk", "mmagic_camss_axi_clk"; clocks = <&clock_mmss clk_camss_jpeg2_clk>, <&clock_mmss clk_camss_jpeg_ahb_clk>, Loading @@ -87,7 +87,7 @@ Example: <&clock_mmss clk_camss_ahb_clk>, <&clock_mmss clk_smmu_jpeg_axi_clk>, <&clock_mmss clk_mmss_mmagic_ahb_clk>, <&clock_mmss clk_mmss_mmagic_axi_clk>, <&clock_gcc clk_mmssnoc_axi_clk>, <&clock_mmss clk_mmagic_camss_axi_clk>; qcom,clock-rates = <266670000 0 0 0 0 0 0 0 0>; qcom,vbif-reg-settings = <0x4 0x1>, Loading Loading @@ -116,7 +116,7 @@ Example: qcom,vdd-names = "mmagic-vdd", "camss-vdd", "vdd"; clock-names = "core_clk", "iface_clk", "bus_clk0", "camss_top_ahb_clk", "camss_ahb_clk", "smmu_jpeg_axi_clk", "mmss_mmagic_ahb_clk", "mmss_mmagic_axi_clk", "mmss_mmagic_ahb_clk", "mmssnoc_axi_clk", "mmagic_camss_axi_clk"; clocks = <&clock_mmss clk_camss_jpeg_dma_clk>, <&clock_mmss clk_camss_jpeg_ahb_clk>, Loading @@ -125,7 +125,7 @@ Example: <&clock_mmss clk_camss_ahb_clk>, <&clock_mmss clk_smmu_jpeg_axi_clk>, <&clock_mmss clk_mmss_mmagic_ahb_clk>, <&clock_mmss clk_mmss_mmagic_axi_clk>, <&clock_gcc clk_mmssnoc_axi_clk>, <&clock_mmss clk_mmagic_camss_axi_clk>; qcom,clock-rates = <266670000 0 0 0 0 0 0 0 0>; qcom,vbif-reg-settings = <0x4 0x1>, Loading
Documentation/devicetree/bindings/media/video/msm-jpegdma.txt +2 −2 Original line number Diff line number Diff line Loading @@ -41,7 +41,7 @@ Example: qcom,vdd-names = "mmagic-vdd", "camss-vdd", "vdd"; clock-names = "core_clk", "iface_clk", "bus_clk0", "camss_top_ahb_clk", "camss_ahb_clk", "smmu_jpeg_axi_clk", "mmss_mmagic_ahb_clk", "mmss_mmagic_axi_clk", "mmss_mmagic_ahb_clk", "mmssnoc_axi_clk", "mmagic_camss_axi_clk"; clocks = <&clock_mmss clk_camss_jpeg_dma_clk>, <&clock_mmss clk_camss_jpeg_ahb_clk>, Loading @@ -50,7 +50,7 @@ Example: <&clock_mmss clk_camss_ahb_clk>, <&clock_mmss clk_smmu_jpeg_axi_clk>, <&clock_mmss clk_mmss_mmagic_ahb_clk>, <&clock_mmss clk_mmss_mmagic_axi_clk>, <&clock_gcc clk_mmssnoc_axi_clk>, <&clock_mmss clk_mmagic_camss_axi_clk>; qcom,clock-rates = <266670000 0 0 0 0 0 0 0 0>, <400000000 0 0 0 0 0 0 0 0>; Loading
arch/arm/boot/dts/qcom/msm-arm-smmu-8996v1.dtsi +12 −12 Original line number Diff line number Diff line Loading @@ -28,11 +28,11 @@ <&clock_mmss clk_mmss_mmagic_cfg_ahb_clk>, <&clock_mmss clk_smmu_jpeg_ahb_clk>, <&clock_mmss clk_smmu_jpeg_axi_clk>, <&clock_mmss clk_mmagic_bimc_axi_clk>, <&clock_gcc clk_mmssnoc_axi_clk>, <&clock_mmss clk_mmagic_camss_axi_clk>; clock-names = "mmagic_ahb_clk", "mmagic_cfg_ahb_clk", "jpeg_ahb_clk", "jpeg_axi_clk", "mmagic_bimc_axi_clk", "mmagic_camss_axi_clk"; "mmssnoc_axi_clk", "mmagic_camss_axi_clk"; #clock-cells = <1>; }; Loading Loading @@ -74,11 +74,11 @@ <&clock_mmss clk_mmss_mmagic_cfg_ahb_clk>, <&clock_mmss clk_smmu_vfe_ahb_clk>, <&clock_mmss clk_smmu_vfe_axi_clk>, <&clock_mmss clk_mmagic_bimc_axi_clk>, <&clock_gcc clk_mmssnoc_axi_clk>, <&clock_mmss clk_mmagic_camss_axi_clk>; clock-names = "mmagic_ahb_clk", "mmagic_cfg_ahb_clk", "vfe_ahb_clk", "vfe_axi_clk", "mmagic_bimc_axi_clk", "mmagic_camss_axi_clk"; "mmssnoc_axi_clk", "mmagic_camss_axi_clk"; #clock-cells = <1>; }; Loading @@ -99,11 +99,11 @@ <&clock_mmss clk_mmss_mmagic_cfg_ahb_clk>, <&clock_mmss clk_smmu_video_ahb_clk>, <&clock_mmss clk_smmu_video_axi_clk>, <&clock_mmss clk_mmagic_bimc_axi_clk>, <&clock_gcc clk_mmssnoc_axi_clk>, <&clock_mmss clk_mmagic_video_axi_clk>; clock-names = "mmagic_ahb_clk", "mmagic_cfg_ahb_clk", "video_ahb_clk", "video_axi_clk", "mmagic_bimc_axi_clk", "mmagic_video_axi_clk"; "mmssnoc_axi_clk", "mmagic_video_axi_clk"; #clock-cells = <1>; }; Loading @@ -124,11 +124,11 @@ <&clock_mmss clk_mmss_mmagic_cfg_ahb_clk>, <&clock_mmss clk_smmu_mdp_ahb_clk>, <&clock_mmss clk_smmu_mdp_axi_clk>, <&clock_mmss clk_mmagic_bimc_axi_clk>, <&clock_gcc clk_mmssnoc_axi_clk>, <&clock_mmss clk_mmagic_mdss_axi_clk>; clock-names = "mmagic_ahb_clk", "mmagic_cfg_ahb_clk", "mdp_ahb_clk", "mdp_axi_clk", "mmagic_bimc_axi_clk", "mmagic_mdss_axi_clk"; "mmssnoc_axi_clk", "mmagic_mdss_axi_clk"; #clock-cells = <1>; }; Loading @@ -147,11 +147,11 @@ <&clock_mmss clk_mmss_mmagic_cfg_ahb_clk>, <&clock_mmss clk_smmu_rot_ahb_clk>, <&clock_mmss clk_smmu_rot_axi_clk>, <&clock_mmss clk_mmagic_bimc_axi_clk>, <&clock_gcc clk_mmssnoc_axi_clk>, <&clock_mmss clk_mmagic_mdss_axi_clk>; clock-names = "mmagic_ahb_clk", "mmagic_cfg_ahb_clk", "rot_ahb_clk", "rot_axi_clk", "mmagic_bimc_axi_clk", "mmagic_mdss_axi_clk"; "mmssnoc_axi_clk", "mmagic_mdss_axi_clk"; #clock-cells = <1>; }; Loading @@ -171,11 +171,11 @@ <&clock_mmss clk_mmss_mmagic_cfg_ahb_clk>, <&clock_mmss clk_smmu_cpp_ahb_clk>, <&clock_mmss clk_smmu_cpp_axi_clk>, <&clock_mmss clk_mmagic_bimc_axi_clk>, <&clock_gcc clk_mmssnoc_axi_clk>, <&clock_mmss clk_mmagic_camss_axi_clk>; clock-names = "mmagic_ahb_clk", "mmagic_cfg_ahb_clk", "cpp_ahb_clk", "cpp_axi_clk", "mmagic_bimc_axi_clk", "mmagic_camss_axi_clk"; "mmssnoc_axi_clk", "mmagic_camss_axi_clk"; #clock-cells = <1>; }; Loading