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Commit f478300f authored by Deepak Katragadda's avatar Deepak Katragadda
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clk: msm: clock-8996: Move MMSSNOC AXI control to RPM 



The MMSSNOC AXI clocks will be controlled by RPM and
not by the HLOS on 8996 going forward. Add support
for the same.
Note that for this to work, the RPM side of the MMSS
NOC support should already be present in the build.

Change-Id: I92890184b61220f509b3042ccbb2a0402352b53e
Signed-off-by: default avatarDeepak Katragadda <dkatraga@codeaurora.org>
parent f0cc8eb8

Documentation/devicetree/bindings/media/video/msm-cpp.txt

+2 −2
Original line number Diff line number Diff line
@@ -77,7 +77,7 @@ Example: 
		camss-vdd-supply = <&gdsc_camss_top>;

		vdd-supply = <&gdsc_cpp>;

		clocks = <&clock_mmss clk_mmss_mmagic_ahb_clk>,

			<&clock_mmss clk_mmss_mmagic_axi_clk>,

			<&clock_gcc  clk_mmssnoc_axi_clk>,

			<&clock_mmss clk_mmagic_camss_axi_clk>,

			<&clock_mmss clk_camss_top_ahb_clk>,

			<&clock_mmss clk_cpp_clk_src>,
@@ -88,7 +88,7 @@ Example: 
			<&clock_mmss clk_camss_ahb_clk>;

			<&clock_mmss clk_smmu_cpp_axi_clk>,

			<&clock_mmss clk_camss_cpp_vbif_ahb_clk>,

		clock-names = "mmss_mmagic_ahb_clk", "mmss_mmagic_axi_clk",

		clock-names = "mmss_mmagic_ahb_clk", "mmssnoc_axi_clk",

			"mmagic_camss_axi_clk", "camss_top_ahb_clk",

			"cpp_core_clk",	"camss_cpp_ahb_clk",

			"camss_cpp_axi_clk", "camss_cpp_clk",

Documentation/devicetree/bindings/media/video/msm-fd.txt

+2 −2
Original line number Diff line number Diff line
@@ -59,7 +59,7 @@ Example: 
        vdd-supply = <&gdsc_fd>;

        qcom,vdd-names = "mmagic-vdd", "camss-vdd", "vdd";

        clocks = <&clock_mmss clk_mmss_mmagic_ahb_clk>,

                <&clock_mmss clk_mmss_mmagic_axi_clk>,

                <&clock_gcc  clk_mmssnoc_axi_clk>,

                <&clock_mmss clk_mmagic_camss_axi_clk>,

                <&clock_mmss clk_camss_top_ahb_clk>,

                <&clock_mmss clk_fd_core_clk_src>,
@@ -71,7 +71,7 @@ Example: 
                <&clock_mmss clk_camss_cpp_axi_clk>,

                <&clock_mmss clk_camss_cpp_vbif_ahb_clk>,

                <&clock_mmss clk_smmu_cpp_ahb_clk>;

        clock-names = "mmss_mmagic_ahb_clk", "mmss_mmagic_axi_clk" ,

        clock-names = "mmss_mmagic_ahb_clk", "mmssnoc_axi_clk" ,

                        "mmagic_camss_axi_clk", "camss_top_ahb_clk",

                        "fd_core_clk_src", "fd_core_clk",

                        "fd_core_uar_clk", "fd_ahb_clk",

Documentation/devicetree/bindings/media/video/msm-jpeg.txt

+6 −6
Original line number Diff line number Diff line
@@ -40,7 +40,7 @@ Example: 
                qcom,vdd-names = "mmagic-vdd", "camss-vdd", "vdd";

		clock-names =  "core_clk", "iface_clk", "bus_clk0",

			       "camss_top_ahb_clk", "camss_ahb_clk", "smmu_jpeg_axi_clk",

                               "mmss_mmagic_ahb_clk", "mmss_mmagic_axi_clk",

                               "mmss_mmagic_ahb_clk", "mmssnoc_axi_clk",

                               "mmagic_camss_axi_clk";

		clocks = <&clock_mmss clk_camss_jpeg0_clk>,

			<&clock_mmss clk_camss_jpeg_ahb_clk>,
@@ -49,7 +49,7 @@ Example: 
			<&clock_mmss clk_camss_ahb_clk>,

			<&clock_mmss clk_smmu_jpeg_axi_clk>,

                        <&clock_mmss clk_mmss_mmagic_ahb_clk>,

                        <&clock_mmss clk_mmss_mmagic_axi_clk>,

                        <&clock_gcc  clk_mmssnoc_axi_clk>,

                        <&clock_mmss clk_mmagic_camss_axi_clk>;

		qcom,clock-rates = <320000000 0 0 0 0 0 0 0 0>;

		qcom,vbif-reg-settings = <0x4 0x1>,
@@ -78,7 +78,7 @@ Example: 
                qcom,vdd-names = "mmagic-vdd", "camss-vdd", "vdd";

		clock-names =  "core_clk", "iface_clk", "bus_clk0",

                               "camss_top_ahb_clk", "camss_ahb_clk", "smmu_jpeg_axi_clk",

                               "mmss_mmagic_ahb_clk", "mmss_mmagic_axi_clk",

                               "mmss_mmagic_ahb_clk", "mmssnoc_axi_clk",

                               "mmagic_camss_axi_clk";

		clocks = <&clock_mmss clk_camss_jpeg2_clk>,

		       <&clock_mmss clk_camss_jpeg_ahb_clk>,
@@ -87,7 +87,7 @@ Example: 
		       <&clock_mmss clk_camss_ahb_clk>,

		       <&clock_mmss clk_smmu_jpeg_axi_clk>,

                       <&clock_mmss clk_mmss_mmagic_ahb_clk>,

                       <&clock_mmss clk_mmss_mmagic_axi_clk>,

                       <&clock_gcc  clk_mmssnoc_axi_clk>,

                       <&clock_mmss clk_mmagic_camss_axi_clk>;

		qcom,clock-rates = <266670000 0 0 0 0 0 0 0 0>;

		qcom,vbif-reg-settings = <0x4 0x1>,
@@ -116,7 +116,7 @@ Example: 
                qcom,vdd-names = "mmagic-vdd", "camss-vdd", "vdd";

		clock-names =  "core_clk", "iface_clk", "bus_clk0",

                               "camss_top_ahb_clk", "camss_ahb_clk", "smmu_jpeg_axi_clk",

                               "mmss_mmagic_ahb_clk", "mmss_mmagic_axi_clk",

                               "mmss_mmagic_ahb_clk", "mmssnoc_axi_clk",

                               "mmagic_camss_axi_clk";

		clocks = <&clock_mmss clk_camss_jpeg_dma_clk>,

			<&clock_mmss clk_camss_jpeg_ahb_clk>,
@@ -125,7 +125,7 @@ Example: 
			<&clock_mmss clk_camss_ahb_clk>,

			<&clock_mmss clk_smmu_jpeg_axi_clk>,

                        <&clock_mmss clk_mmss_mmagic_ahb_clk>,

                        <&clock_mmss clk_mmss_mmagic_axi_clk>,

                        <&clock_gcc  clk_mmssnoc_axi_clk>,

                        <&clock_mmss clk_mmagic_camss_axi_clk>;

		qcom,clock-rates = <266670000 0 0 0 0 0 0 0 0>;

		qcom,vbif-reg-settings = <0x4 0x1>,

Documentation/devicetree/bindings/media/video/msm-jpegdma.txt

+2 −2
Original line number Diff line number Diff line
@@ -41,7 +41,7 @@ Example: 
		qcom,vdd-names = "mmagic-vdd", "camss-vdd", "vdd";

		clock-names =  "core_clk", "iface_clk", "bus_clk0",

				"camss_top_ahb_clk", "camss_ahb_clk", "smmu_jpeg_axi_clk",

				"mmss_mmagic_ahb_clk", "mmss_mmagic_axi_clk",

				"mmss_mmagic_ahb_clk", "mmssnoc_axi_clk",

				"mmagic_camss_axi_clk";

		clocks = <&clock_mmss clk_camss_jpeg_dma_clk>,

			<&clock_mmss clk_camss_jpeg_ahb_clk>,
@@ -50,7 +50,7 @@ Example: 
			<&clock_mmss clk_camss_ahb_clk>,

			<&clock_mmss clk_smmu_jpeg_axi_clk>,

			<&clock_mmss clk_mmss_mmagic_ahb_clk>,

			<&clock_mmss clk_mmss_mmagic_axi_clk>,

			<&clock_gcc  clk_mmssnoc_axi_clk>,

			<&clock_mmss clk_mmagic_camss_axi_clk>;

		qcom,clock-rates = <266670000 0 0 0 0 0 0 0 0>,

				<400000000 0 0 0 0 0 0 0 0>;

arch/arm/boot/dts/qcom/msm-arm-smmu-8996v1.dtsi

+12 −12
Original line number Diff line number Diff line
@@ -28,11 +28,11 @@ 
		<&clock_mmss clk_mmss_mmagic_cfg_ahb_clk>,

		<&clock_mmss clk_smmu_jpeg_ahb_clk>,

		<&clock_mmss clk_smmu_jpeg_axi_clk>,

		<&clock_mmss clk_mmagic_bimc_axi_clk>,

		<&clock_gcc clk_mmssnoc_axi_clk>,

		<&clock_mmss clk_mmagic_camss_axi_clk>;

	clock-names = "mmagic_ahb_clk", "mmagic_cfg_ahb_clk",

		"jpeg_ahb_clk", "jpeg_axi_clk",

		"mmagic_bimc_axi_clk", "mmagic_camss_axi_clk";

		"mmssnoc_axi_clk", "mmagic_camss_axi_clk";

	#clock-cells = <1>;

};
@@ -74,11 +74,11 @@ 
		<&clock_mmss clk_mmss_mmagic_cfg_ahb_clk>,

		<&clock_mmss clk_smmu_vfe_ahb_clk>,

		<&clock_mmss clk_smmu_vfe_axi_clk>,

		<&clock_mmss clk_mmagic_bimc_axi_clk>,

		<&clock_gcc clk_mmssnoc_axi_clk>,

		<&clock_mmss clk_mmagic_camss_axi_clk>;

	clock-names = "mmagic_ahb_clk", "mmagic_cfg_ahb_clk",

		"vfe_ahb_clk", "vfe_axi_clk",

		"mmagic_bimc_axi_clk", "mmagic_camss_axi_clk";

		"mmssnoc_axi_clk", "mmagic_camss_axi_clk";

	#clock-cells = <1>;

};
@@ -99,11 +99,11 @@ 
		<&clock_mmss clk_mmss_mmagic_cfg_ahb_clk>,

		<&clock_mmss clk_smmu_video_ahb_clk>,

		<&clock_mmss clk_smmu_video_axi_clk>,

		<&clock_mmss clk_mmagic_bimc_axi_clk>,

		<&clock_gcc clk_mmssnoc_axi_clk>,

		<&clock_mmss clk_mmagic_video_axi_clk>;

	clock-names = "mmagic_ahb_clk", "mmagic_cfg_ahb_clk",

		"video_ahb_clk", "video_axi_clk",

		"mmagic_bimc_axi_clk", "mmagic_video_axi_clk";

		"mmssnoc_axi_clk", "mmagic_video_axi_clk";

	#clock-cells = <1>;

};
@@ -124,11 +124,11 @@ 
		<&clock_mmss clk_mmss_mmagic_cfg_ahb_clk>,

		<&clock_mmss clk_smmu_mdp_ahb_clk>,

		<&clock_mmss clk_smmu_mdp_axi_clk>,

		<&clock_mmss clk_mmagic_bimc_axi_clk>,

		<&clock_gcc clk_mmssnoc_axi_clk>,

		<&clock_mmss clk_mmagic_mdss_axi_clk>;

	clock-names = "mmagic_ahb_clk", "mmagic_cfg_ahb_clk",

		"mdp_ahb_clk", "mdp_axi_clk",

		"mmagic_bimc_axi_clk", "mmagic_mdss_axi_clk";

		"mmssnoc_axi_clk", "mmagic_mdss_axi_clk";

	#clock-cells = <1>;

};
@@ -147,11 +147,11 @@ 
		<&clock_mmss clk_mmss_mmagic_cfg_ahb_clk>,

		<&clock_mmss clk_smmu_rot_ahb_clk>,

		<&clock_mmss clk_smmu_rot_axi_clk>,

		<&clock_mmss clk_mmagic_bimc_axi_clk>,

		<&clock_gcc clk_mmssnoc_axi_clk>,

		<&clock_mmss clk_mmagic_mdss_axi_clk>;

	clock-names = "mmagic_ahb_clk", "mmagic_cfg_ahb_clk",

		"rot_ahb_clk", "rot_axi_clk",

		"mmagic_bimc_axi_clk", "mmagic_mdss_axi_clk";

		"mmssnoc_axi_clk", "mmagic_mdss_axi_clk";

	#clock-cells = <1>;

};
@@ -171,11 +171,11 @@ 
		<&clock_mmss clk_mmss_mmagic_cfg_ahb_clk>,

		<&clock_mmss clk_smmu_cpp_ahb_clk>,

		<&clock_mmss clk_smmu_cpp_axi_clk>,

		<&clock_mmss clk_mmagic_bimc_axi_clk>,

		<&clock_gcc clk_mmssnoc_axi_clk>,

		<&clock_mmss clk_mmagic_camss_axi_clk>;

	clock-names = "mmagic_ahb_clk", "mmagic_cfg_ahb_clk",

		"cpp_ahb_clk", "cpp_axi_clk",

		"mmagic_bimc_axi_clk", "mmagic_camss_axi_clk";

		"mmssnoc_axi_clk", "mmagic_camss_axi_clk";

	#clock-cells = <1>;

};