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Commit 242e6fa2 authored by Trilok Soni's avatar Trilok Soni
Browse files

irqchip: gicv3: Add GICv3 access control Kconfig option



Some SOCs(System-on-chip) S/W configurations restricts the access
to particular set of the GIC registers to prevent invalid
accesses for the security reasons. Provide a configuration
option for the GICv3 driver and also restrict the access
of the GICR_WAKER registers from the non-secure world.

If this Kconfig option is not selected then it means that
access control configuration is enabled from the secure world.

CRs-Fixed: 958251
Change-Id: I91f06484b6b6bf58d05e6b621ee84610a71fe3e7
Signed-off-by: default avatarTrilok Soni <tsoni@codeaurora.org>
parent 60d83900
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+12 −0
Original line number Diff line number Diff line
@@ -38,6 +38,18 @@ config ARM_GIC_V3_ACL
	  Access to GIC ITS address space is controlled by EL2.
	  Kernel has no permission to access ITS

config ARM_GIC_V3_NO_ACCESS_CONTROL
	bool "GICv3 No Access Control Configuration"
	depends on ARM_GIC_V3
	help
	  On some SOCs with the access control configurations it is
	  not allowed to access certain set of the GIC registers
	  from non-secure world. Provide a common flag to protect
	  those functionalities and compile them out for such
	  configurations, so that specific registers are not touched.

	  For production kernels, you should say 'N' here.

config ARM_NVIC
	bool
	select IRQ_DOMAIN
+4 −0
Original line number Diff line number Diff line
@@ -178,6 +178,7 @@ static void gic_enable_sre(void)
		pr_err("GIC: unable to set SRE (disabled at EL2), panic ahead\n");
}

#ifdef CONFIG_ARM_GIC_V3_NO_ACCESS_CONTROL
static void gic_enable_redist(bool enable)
{
	void __iomem *rbase;
@@ -211,6 +212,9 @@ static void gic_enable_redist(bool enable)
		pr_err_ratelimited("redistributor failed to %s...\n",
				   enable ? "wakeup" : "sleep");
}
#else
static void gic_enable_redist(bool enable) { }
#endif

/*
 * Routines to disable, enable, EOI and route interrupts