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Commit 21d2e285 authored by Jin Li's avatar Jin Li
Browse files

drm/sde: add wider hdmi support 



When HDMI resolution is bigger than 2560 pixel of width, driver
needs to use two hardware pipes to support it. Use virtual plane
to support this feature.

Change-Id: I4ae403f5ad86e257defc3c6a720d8fd954d92d79
Signed-off-by: default avatarJin Li <jinl@codeaurora.org>
parent 623f47b7

Documentation/devicetree/bindings/drm/msm/mdp.txt

+26 −0
Original line number Diff line number Diff line
@@ -18,6 +18,15 @@ Required properties: 


Optional properties:

- gpus: phandle for gpu device

- qcom,sde-plane-id-map: plane id mapping for virtual plane.

- qcom,sde-plane-id: each virtual plane mapping node.

- qcom,display-type: display type this plane is mapped to. It could be

 "primary", "secondary" and "tertiary".

- qcom,plane-name: plane name array for this virtual plane. It could be

 "rgb0", "rgb1", "rgb2", "rgb3", "vig0", "vig1", "vig2", "vig3", "dma0", "dma1",

 "dma2", "dma3", "cursor0", "cursor1".

- qcom,plane-type: virtual plane type. It could be "primary", "overlay",

 "cursor".



Example:
@@ -44,5 +53,22 @@ Example: 
		    <&mmcc TV_SRC>,

		    <&mmcc HDMI_TV_CLK>,

		    <&mmcc MDP_TV_CLK>;

		qcom,sde-plane-id-map {

			qcom,sde-plane-id@0 {

				qcom,display-type = "primary";

				qcom,plane-name = "rgb0", "rgb1";

				qcom,plane-type = "primary";

			};

			qcom,sde-plane-id@1 {

				qcom,display-type = "primary";

				qcom,plane-name = "vig0", "vig1";

				qcom,plane-type = "overlay";

			};

			qcom,sde-plane-id@2 {

				qcom,display-type = "primary";

				qcom,plane-name = "cursor0", "cursor1";

				qcom,plane-type = "cursor";

			};

		};

	};

};

drivers/gpu/drm/msm/hdmi-staging/sde_hdmi.c

+3 −2
Original line number Diff line number Diff line
@@ -475,6 +475,7 @@ int sde_hdmi_get_info(struct msm_display_info *info, 
		return -EINVAL;

	}



	DBG("");

	mutex_lock(&hdmi_display->display_lock);



	info->intf_type = DRM_MODE_CONNECTOR_HDMIA;
@@ -483,8 +484,8 @@ int sde_hdmi_get_info(struct msm_display_info *info, 
	info->is_connected = true;

	info->capabilities = MSM_DISPLAY_CAP_HOT_PLUG | MSM_DISPLAY_CAP_EDID |

				MSM_DISPLAY_CAP_VID_MODE;

	info->max_width = 1920;

	info->max_height = 1080;

	info->max_width = 4096;

	info->max_height = 2160;

	info->compression = MSM_DISPLAY_COMPRESS_NONE;



	mutex_unlock(&hdmi_display->display_lock);

drivers/gpu/drm/msm/hdmi/hdmi.xml.h

+9 −9
Original line number Diff line number Diff line
@@ -462,13 +462,13 @@ static inline uint32_t HDMI_DDC_REF_REFTIMER(uint32_t val) 
#define REG_HDMI_CEC_RD_FILTER					0x000002b0



#define REG_HDMI_ACTIVE_HSYNC					0x000002b4

#define HDMI_ACTIVE_HSYNC_START__MASK				0x00000fff

#define HDMI_ACTIVE_HSYNC_START__MASK				0x00001fff

#define HDMI_ACTIVE_HSYNC_START__SHIFT				0

static inline uint32_t HDMI_ACTIVE_HSYNC_START(uint32_t val)

{

	return ((val) << HDMI_ACTIVE_HSYNC_START__SHIFT) & HDMI_ACTIVE_HSYNC_START__MASK;

}

#define HDMI_ACTIVE_HSYNC_END__MASK				0x0fff0000

#define HDMI_ACTIVE_HSYNC_END__MASK				0x1fff0000

#define HDMI_ACTIVE_HSYNC_END__SHIFT				16

static inline uint32_t HDMI_ACTIVE_HSYNC_END(uint32_t val)

{
@@ -476,13 +476,13 @@ static inline uint32_t HDMI_ACTIVE_HSYNC_END(uint32_t val) 
}



#define REG_HDMI_ACTIVE_VSYNC					0x000002b8

#define HDMI_ACTIVE_VSYNC_START__MASK				0x00000fff

#define HDMI_ACTIVE_VSYNC_START__MASK				0x00001fff

#define HDMI_ACTIVE_VSYNC_START__SHIFT				0

static inline uint32_t HDMI_ACTIVE_VSYNC_START(uint32_t val)

{

	return ((val) << HDMI_ACTIVE_VSYNC_START__SHIFT) & HDMI_ACTIVE_VSYNC_START__MASK;

}

#define HDMI_ACTIVE_VSYNC_END__MASK				0x0fff0000

#define HDMI_ACTIVE_VSYNC_END__MASK				0x1fff0000

#define HDMI_ACTIVE_VSYNC_END__SHIFT				16

static inline uint32_t HDMI_ACTIVE_VSYNC_END(uint32_t val)

{
@@ -490,13 +490,13 @@ static inline uint32_t HDMI_ACTIVE_VSYNC_END(uint32_t val) 
}



#define REG_HDMI_VSYNC_ACTIVE_F2				0x000002bc

#define HDMI_VSYNC_ACTIVE_F2_START__MASK			0x00000fff

#define HDMI_VSYNC_ACTIVE_F2_START__MASK			0x00001fff

#define HDMI_VSYNC_ACTIVE_F2_START__SHIFT			0

static inline uint32_t HDMI_VSYNC_ACTIVE_F2_START(uint32_t val)

{

	return ((val) << HDMI_VSYNC_ACTIVE_F2_START__SHIFT) & HDMI_VSYNC_ACTIVE_F2_START__MASK;

}

#define HDMI_VSYNC_ACTIVE_F2_END__MASK				0x0fff0000

#define HDMI_VSYNC_ACTIVE_F2_END__MASK				0x1fff0000

#define HDMI_VSYNC_ACTIVE_F2_END__SHIFT				16

static inline uint32_t HDMI_VSYNC_ACTIVE_F2_END(uint32_t val)

{
@@ -504,13 +504,13 @@ static inline uint32_t HDMI_VSYNC_ACTIVE_F2_END(uint32_t val) 
}



#define REG_HDMI_TOTAL						0x000002c0

#define HDMI_TOTAL_H_TOTAL__MASK				0x00000fff

#define HDMI_TOTAL_H_TOTAL__MASK				0x00001fff

#define HDMI_TOTAL_H_TOTAL__SHIFT				0

static inline uint32_t HDMI_TOTAL_H_TOTAL(uint32_t val)

{

	return ((val) << HDMI_TOTAL_H_TOTAL__SHIFT) & HDMI_TOTAL_H_TOTAL__MASK;

}

#define HDMI_TOTAL_V_TOTAL__MASK				0x0fff0000

#define HDMI_TOTAL_V_TOTAL__MASK				0x1fff0000

#define HDMI_TOTAL_V_TOTAL__SHIFT				16

static inline uint32_t HDMI_TOTAL_V_TOTAL(uint32_t val)

{
@@ -518,7 +518,7 @@ static inline uint32_t HDMI_TOTAL_V_TOTAL(uint32_t val) 
}



#define REG_HDMI_VSYNC_TOTAL_F2					0x000002c4

#define HDMI_VSYNC_TOTAL_F2_V_TOTAL__MASK			0x00000fff

#define HDMI_VSYNC_TOTAL_F2_V_TOTAL__MASK			0x00001fff

#define HDMI_VSYNC_TOTAL_F2_V_TOTAL__SHIFT			0

static inline uint32_t HDMI_VSYNC_TOTAL_F2_V_TOTAL(uint32_t val)

{

drivers/gpu/drm/msm/sde/sde_crtc.c

+21 −5
Original line number Diff line number Diff line
@@ -186,27 +186,39 @@ static u32 blend_config_per_mixer(struct drm_crtc *crtc, 


	drm_atomic_crtc_for_each_plane(plane, crtc) {

		pstate = to_sde_plane_state(plane->state);

		/*

		 * Always program right lm first if in dual mixer mode,

		 * it could be overwrote later.

		 */

		if (sde_crtc->num_mixers == CRTC_DUAL_MIXERS)

			sde_crtc->stage_cfg.stage[pstate->stage][1] =

				sde_plane_pipe(plane, 1);

		is_right_lm = plane->state->crtc_x >= crtc_split_width ?

						true : false;

		sde_crtc->stage_cfg.stage[pstate->stage][is_right_lm] =

			sde_plane_pipe(plane);

			sde_plane_pipe(plane, is_right_lm ? 1 : 0);



		/* stage layer on right lm if it crosses the boundary */

		if (plane->state->crtc_x + plane->state->crtc_w >

							crtc_split_width)

			sde_crtc->stage_cfg.stage[pstate->stage][is_right_lm] =

					sde_plane_pipe(plane);

				sde_plane_pipe(plane, is_right_lm ? 1 : 0);



		SDE_DEBUG("crtc_id %d pipe %d at stage %d\n",

			crtc->base.id, sde_plane_pipe(plane), pstate->stage);

			crtc->base.id,

			sde_plane_pipe(plane, is_right_lm ? 1 : 0),

			pstate->stage);



		/**

		 * cache the flushmask for this layer

		 * sourcesplit is always enabled, so this layer will

		 * be staged on both the mixers

		 */

		if (sde_crtc->num_mixers == CRTC_DUAL_MIXERS)

			ctl->ops.get_bitmask_sspp(ctl, &flush_mask,

				sde_plane_pipe(plane));

					sde_plane_pipe(plane, 1));

		ctl->ops.get_bitmask_sspp(ctl, &flush_mask,

				sde_plane_pipe(plane, is_right_lm ? 1 : 0));



		/* blend config */

		sde_crtc_get_blend_cfg(&blend, pstate);
@@ -471,6 +483,7 @@ static void _sde_crtc_setup_mixer_for_encoder( 
	int i;

	struct sde_rm_hw_iter lm_iter, ctl_iter;



	DBG("");

	sde_rm_init_hw_iter(&lm_iter, enc->base.id, SDE_HW_BLK_LM);

	sde_rm_init_hw_iter(&ctl_iter, enc->base.id, SDE_HW_BLK_CTL);
@@ -542,6 +555,8 @@ static void sde_crtc_atomic_begin(struct drm_crtc *crtc, 
	sde_crtc = to_sde_crtc(crtc);

	dev = crtc->dev;



	DBG("crtc:%d num_mixers=%d\n", sde_crtc->drm_crtc_id,

		sde_crtc->num_mixers);

	if (!sde_crtc->num_mixers)

		_sde_crtc_setup_mixers(crtc);
@@ -1226,6 +1241,7 @@ struct drm_crtc *sde_crtc_init(struct drm_device *dev, 


	sde_crtc_install_properties(crtc);



	SDE_DEBUG("%s: successfully initialized crtc\n", sde_crtc->name);

	SDE_DEBUG("%s: successfully initialized crtc=%p\n",

			sde_crtc->name, crtc);

	return crtc;

}

drivers/gpu/drm/msm/sde/sde_encoder.c

+2 −2
Original line number Diff line number Diff line
@@ -703,7 +703,7 @@ static int sde_encoder_setup_display(struct sde_encoder_virt *sde_enc, 


	sde_enc->display_num_of_h_tiles = disp_info->num_of_h_tiles;



	DBG("dsi_info->num_of_h_tiles %d", disp_info->num_of_h_tiles);

	DBG("disp_info->num_of_h_tiles %d", disp_info->num_of_h_tiles);



	for (i = 0; i < disp_info->num_of_h_tiles && !ret; i++) {

		/*
@@ -743,7 +743,7 @@ static int sde_encoder_setup_display(struct sde_encoder_virt *sde_enc, 
					controller_id);

			if (phys_params.intf_idx == INTF_MAX) {

				DRM_ERROR(

					"Error: could not get writeback: type %d, id %d\n",

					"Error: could not get physical: type %d, id %d\n",

					intf_type, controller_id);

				ret = -EINVAL;

			}