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Commit 1e0d48c2 authored by Matt Wagantall's avatar Matt Wagantall
Browse files

Merge tag 'v3.18.2' into msm-3.18 



This is the 3.18.2 stable release

Resolve conflicts in arch_timer code related to inclusion of the
local change 22953ce9 ("ARM: arch_timer: resurrect cntpct for
MSM users") and upstream change 82c236bc ("clocksource:
arch_timer: Fix code to use physical timers when requested"), as
well as a trivial context conflict in mmc/card/block.c.

Conflicts:
	arch/arm/include/asm/arch_timer.h
	arch/arm64/include/asm/arch_timer.h
	drivers/clocksource/arm_arch_timer.c
	drivers/mmc/card/block.c

Change-Id: I453acfd66eb856181c2a497dcdb235ce39db9292
Signed-off-by: default avatarMatt Wagantall <mattw@codeaurora.org>
parents a927120b e609d3fc

Makefile

+1 −1
Original line number Diff line number Diff line 
VERSION = 3

PATCHLEVEL = 18

SUBLEVEL = 1

SUBLEVEL = 2

EXTRAVERSION =

NAME = Shuffling Zombie Juror

arch/arm/boot/dts/armada-370-db.dts

+0 −24
Original line number Diff line number Diff line
@@ -102,30 +102,6 @@ 
				broken-cd;

			};



			pinctrl {

				/*

				 * These pins might be muxed as I2S by

				 * the bootloader, but it conflicts

				 * with the real I2S pins that are

				 * muxed using i2s_pins. We must mux

				 * those pins to a function other than

				 * I2S.

				 */

				pinctrl-0 = <&hog_pins1 &hog_pins2>;

				pinctrl-names = "default";



				hog_pins1: hog-pins1 {

					marvell,pins = "mpp6",  "mpp8", "mpp10",

						       "mpp12", "mpp13";

					marvell,function = "gpio";

				};



				hog_pins2: hog-pins2 {

					marvell,pins = "mpp5", "mpp7", "mpp9";

					marvell,function = "gpo";

				};

			};



			usb@50000 {

				status = "okay";

			};

arch/arm/boot/dts/armada-370.dtsi

+5 −5
Original line number Diff line number Diff line
@@ -106,11 +106,6 @@ 
				reg = <0x11100 0x20>;

			};



			system-controller@18200 {

				compatible = "marvell,armada-370-xp-system-controller";

				reg = <0x18200 0x100>;

			};



			pinctrl {

				compatible = "marvell,mv88f6710-pinctrl";

				reg = <0x18000 0x38>;
@@ -205,6 +200,11 @@ 
				interrupts = <91>;

			};



			system-controller@18200 {

				compatible = "marvell,armada-370-xp-system-controller";

				reg = <0x18200 0x100>;

			};



			gateclk: clock-gating-control@18220 {

				compatible = "marvell,armada-370-gating-clock";

				reg = <0x18220 0x4>;

arch/arm/mach-mvebu/coherency.c

+30 −14
Original line number Diff line number Diff line
@@ -361,27 +361,43 @@ static int coherency_type(void) 
{

	struct device_node *np;

	const struct of_device_id *match;

	int type;



	/*

	 * The coherency fabric is needed:

	 * - For coherency between processors on Armada XP, so only

	 *   when SMP is enabled.

	 * - For coherency between the processor and I/O devices, but

	 *   this coherency requires many pre-requisites (write

	 *   allocate cache policy, shareable pages, SMP bit set) that

	 *   are only meant in SMP situations.

	 *

	 * Note that this means that on Armada 370, there is currently

	 * no way to use hardware I/O coherency, because even when

	 * CONFIG_SMP is enabled, is_smp() returns false due to the

	 * Armada 370 being a single-core processor. To lift this

	 * limitation, we would have to find a way to make the cache

	 * policy set to write-allocate (on all Armada SoCs), and to

	 * set the shareable attribute in page tables (on all Armada

	 * SoCs except the Armada 370). Unfortunately, such decisions

	 * are taken very early in the kernel boot process, at a point

	 * where we don't know yet on which SoC we are running.



	 */

	if (!is_smp())

		return COHERENCY_FABRIC_TYPE_NONE;



	np = of_find_matching_node_and_match(NULL, of_coherency_table, &match);

	if (np) {

		int type = (int) match->data;

	if (!np)

		return COHERENCY_FABRIC_TYPE_NONE;



		/* Armada 370/XP coherency works in both UP and SMP */

		if (type == COHERENCY_FABRIC_TYPE_ARMADA_370_XP)

			return type;

	type = (int) match->data;



		/* Armada 375 coherency works only on SMP */

		else if (type == COHERENCY_FABRIC_TYPE_ARMADA_375 && is_smp())

			return type;

	of_node_put(np);



		/* Armada 380 coherency works only on SMP */

		else if (type == COHERENCY_FABRIC_TYPE_ARMADA_380 && is_smp())

	return type;

}



	return COHERENCY_FABRIC_TYPE_NONE;

}



int coherency_available(void)

{

	return coherency_type() != COHERENCY_FABRIC_TYPE_NONE;

arch/arm/mach-mvebu/coherency_ll.S

+19 −2
Original line number Diff line number Diff line
@@ -24,7 +24,10 @@ 
#include <asm/cp15.h>



	.text

/* Returns the coherency base address in r1 (r0 is untouched) */

/*

 * Returns the coherency base address in r1 (r0 is untouched), or 0 if

 * the coherency fabric is not enabled.

 */

ENTRY(ll_get_coherency_base)

	mrc	p15, 0, r1, c1, c0, 0

	tst	r1, #CR_M @ Check MMU bit enabled
@@ -32,8 +35,13 @@ ENTRY(ll_get_coherency_base) 


	/*

	 * MMU is disabled, use the physical address of the coherency

	 * base address.

	 * base address. However, if the coherency fabric isn't mapped

	 * (i.e its virtual address is zero), it means coherency is

	 * not enabled, so we return 0.

	 */

	ldr	r1, =coherency_base

	cmp	r1, #0

	beq	2f

	adr	r1, 3f

	ldr	r3, [r1]

	ldr	r1, [r1, r3]
@@ -85,6 +93,9 @@ ENTRY(ll_add_cpu_to_smp_group) 
	 */

	mov 	r0, lr

	bl	ll_get_coherency_base

	/* Bail out if the coherency is not enabled */

	cmp	r1, #0

	reteq	r0

	bl	ll_get_coherency_cpumask

	mov 	lr, r0

	add	r0, r1, #ARMADA_XP_CFB_CFG_REG_OFFSET
@@ -107,6 +118,9 @@ ENTRY(ll_enable_coherency) 
	 */

	mov r0, lr

	bl	ll_get_coherency_base

	/* Bail out if the coherency is not enabled */

	cmp	r1, #0

	reteq	r0

	bl	ll_get_coherency_cpumask

	mov lr, r0

	add	r0, r1, #ARMADA_XP_CFB_CTL_REG_OFFSET
@@ -131,6 +145,9 @@ ENTRY(ll_disable_coherency) 
	 */

	mov 	r0, lr

	bl	ll_get_coherency_base

	/* Bail out if the coherency is not enabled */

	cmp	r1, #0

	reteq	r0

	bl	ll_get_coherency_cpumask

	mov 	lr, r0

	add	r0, r1, #ARMADA_XP_CFB_CTL_REG_OFFSET