Loading drivers/clk/msm/clock-gcc-cobalt.c +0 −12 Original line number Diff line number Diff line Loading @@ -1777,17 +1777,6 @@ static struct branch_clk gcc_mmss_noc_cfg_ahb_clk = { }, }; static struct branch_clk gcc_mmss_qm_ahb_clk = { .cbcr_reg = GCC_MMSS_QM_AHB_CBCR, .has_sibling = 1, .base = &virt_base, .c = { .dbg_name = "gcc_mmss_qm_ahb_clk", .ops = &clk_ops_branch, CLK_INIT(gcc_mmss_qm_ahb_clk.c), }, }; static struct branch_clk gcc_mmss_sys_noc_axi_clk = { .cbcr_reg = GCC_MMSS_SYS_NOC_AXI_CBCR, .has_sibling = 1, Loading Loading @@ -2612,7 +2601,6 @@ static struct clk_lookup msm_clocks_gcc_cobalt[] = { CLK_LIST(gcc_hmss_dvm_bus_clk), CLK_LIST(gcc_hmss_rbcpr_clk), CLK_LIST(gcc_mmss_noc_cfg_ahb_clk), CLK_LIST(gcc_mmss_qm_ahb_clk), CLK_LIST(gcc_mmss_sys_noc_axi_clk), CLK_LIST(gcc_pcie_0_aux_clk), CLK_LIST(gcc_pcie_0_cfg_ahb_clk), Loading include/dt-bindings/clock/msm-clocks-cobalt.h +0 −2 Original line number Diff line number Diff line Loading @@ -208,8 +208,6 @@ #define clk_gcc_hmss_rbcpr_clk 0x699183be #define clk_hmss_gpll0_clk_src 0x17eb05d0 #define clk_hmss_gpll4_clk_src 0x20456cae #define clk_gcc_mmss_qm_ahb_clk 0xc759178c #define clk_gcc_mmss_qm_core_clk 0xa3412619 #define clk_gcc_mmss_sys_noc_axi_clk 0x4467b15b #define clk_gcc_mss_at_clk 0x1692c5aa #define clk_nav_gcc_dbg_clk 0x2221c544 Loading include/dt-bindings/clock/msm-clocks-hwio-cobalt.h +0 −2 Original line number Diff line number Diff line Loading @@ -175,8 +175,6 @@ #define GCC_HMSS_RBCPR_CBCR 0x48008 #define GCC_MMSS_SYS_NOC_AXI_CBCR 0x09000 #define GCC_MMSS_NOC_CFG_AHB_CBCR 0x09004 #define GCC_MMSS_QM_AHB_CBCR 0x09030 #define GCC_MMSS_QM_CORE_CBCR 0x0900C #define GCC_PCIE_0_SLV_AXI_CBCR 0x6B008 #define GCC_PCIE_0_MSTR_AXI_CBCR 0x6B00C #define GCC_PCIE_0_CFG_AHB_CBCR 0x6B010 Loading Loading
drivers/clk/msm/clock-gcc-cobalt.c +0 −12 Original line number Diff line number Diff line Loading @@ -1777,17 +1777,6 @@ static struct branch_clk gcc_mmss_noc_cfg_ahb_clk = { }, }; static struct branch_clk gcc_mmss_qm_ahb_clk = { .cbcr_reg = GCC_MMSS_QM_AHB_CBCR, .has_sibling = 1, .base = &virt_base, .c = { .dbg_name = "gcc_mmss_qm_ahb_clk", .ops = &clk_ops_branch, CLK_INIT(gcc_mmss_qm_ahb_clk.c), }, }; static struct branch_clk gcc_mmss_sys_noc_axi_clk = { .cbcr_reg = GCC_MMSS_SYS_NOC_AXI_CBCR, .has_sibling = 1, Loading Loading @@ -2612,7 +2601,6 @@ static struct clk_lookup msm_clocks_gcc_cobalt[] = { CLK_LIST(gcc_hmss_dvm_bus_clk), CLK_LIST(gcc_hmss_rbcpr_clk), CLK_LIST(gcc_mmss_noc_cfg_ahb_clk), CLK_LIST(gcc_mmss_qm_ahb_clk), CLK_LIST(gcc_mmss_sys_noc_axi_clk), CLK_LIST(gcc_pcie_0_aux_clk), CLK_LIST(gcc_pcie_0_cfg_ahb_clk), Loading
include/dt-bindings/clock/msm-clocks-cobalt.h +0 −2 Original line number Diff line number Diff line Loading @@ -208,8 +208,6 @@ #define clk_gcc_hmss_rbcpr_clk 0x699183be #define clk_hmss_gpll0_clk_src 0x17eb05d0 #define clk_hmss_gpll4_clk_src 0x20456cae #define clk_gcc_mmss_qm_ahb_clk 0xc759178c #define clk_gcc_mmss_qm_core_clk 0xa3412619 #define clk_gcc_mmss_sys_noc_axi_clk 0x4467b15b #define clk_gcc_mss_at_clk 0x1692c5aa #define clk_nav_gcc_dbg_clk 0x2221c544 Loading
include/dt-bindings/clock/msm-clocks-hwio-cobalt.h +0 −2 Original line number Diff line number Diff line Loading @@ -175,8 +175,6 @@ #define GCC_HMSS_RBCPR_CBCR 0x48008 #define GCC_MMSS_SYS_NOC_AXI_CBCR 0x09000 #define GCC_MMSS_NOC_CFG_AHB_CBCR 0x09004 #define GCC_MMSS_QM_AHB_CBCR 0x09030 #define GCC_MMSS_QM_CORE_CBCR 0x0900C #define GCC_PCIE_0_SLV_AXI_CBCR 0x6B008 #define GCC_PCIE_0_MSTR_AXI_CBCR 0x6B00C #define GCC_PCIE_0_CFG_AHB_CBCR 0x6B010 Loading