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Commit 4fad5baf authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "clk: msm: clock: Add support for programming the DCC AHB clock register"

parents 15b79dc6 366772d4

drivers/clk/msm/clock-gcc-cobalt.c

+13 −0
Original line number Diff line number Diff line
@@ -2267,6 +2267,17 @@ static struct branch_clk gcc_mss_snoc_axi_clk = { 
	},

};



static struct branch_clk gcc_dcc_ahb_clk = {

	.cbcr_reg = GCC_DCC_AHB_CBCR,

	.has_sibling = 1,

	.base = &virt_base,

	.c = {

		.dbg_name = "gcc_dcc_ahb_clk",

		.ops = &clk_ops_branch,

		CLK_INIT(gcc_dcc_ahb_clk.c),

	},

};



static struct branch_clk hlos1_vote_lpass_core_smmu_clk = {

	.cbcr_reg = GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CBCR,

	.has_sibling = 0,
@@ -2392,6 +2403,7 @@ static struct mux_clk gcc_debug_mux = { 
		{ &gcc_ufs_rx_symbol_0_clk.c, 0x00ed },

		{ &gcc_ufs_unipro_core_clk.c, 0x00f0 },

		{ &gcc_ufs_ice_core_clk.c, 0x00f1 },

		{ &gcc_dcc_ahb_clk.c, 0x0119 },

		{ &ipa_clk.c, 0x011b },

		{ &gcc_mss_cfg_ahb_clk.c, 0x011f },

		{ &gcc_mss_q6_bimc_axi_clk.c, 0x0124 },
@@ -2647,6 +2659,7 @@ static struct clk_lookup msm_clocks_gcc_cobalt[] = { 
	CLK_LIST(gcc_rx1_usb2_clkref_clk),

	CLK_LIST(gcc_ufs_clkref_clk),

	CLK_LIST(gcc_usb3_clkref_clk),

	CLK_LIST(gcc_dcc_ahb_clk),

	CLK_LIST(hlos1_vote_lpass_core_smmu_clk),

	CLK_LIST(hlos1_vote_lpass_adsp_smmu_clk),

};

include/dt-bindings/clock/msm-clocks-cobalt.h

+1 −0
Original line number Diff line number Diff line
@@ -261,6 +261,7 @@ 
#define clk_gcc_qusb2phy_sec_reset		0x3f3a87d0

#define clk_gcc_mmss_noc_cfg_ahb_clk		0xb41a9d99

#define clk_gcc_wcss_shdreg_ahb_clk		0x33459c85

#define clk_gcc_dcc_ahb_clk			0xfa14a88c

#define clk_hlos1_vote_lpass_core_smmu_clk	0x3aaa1743

#define clk_hlos1_vote_lpass_adsp_smmu_clk	0xc76f702f

#define clk_gcc_mss_cfg_ahb_clk			0x111cde81

include/dt-bindings/clock/msm-clocks-hwio-cobalt.h

+1 −0
Original line number Diff line number Diff line
@@ -227,6 +227,7 @@ 
#define GCC_MSS_Q6_BIMC_AXI_CBCR				0x8A040

#define GCC_MSS_MNOC_BIMC_AXI_CBCR				0x8A004

#define GCC_MSS_SNOC_AXI_CBCR					0x8A03C

#define GCC_DCC_AHB_CBCR					0x84004

#define GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CBCR			0x7D010

#define GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CBCR			0x7D014