Loading arch/arm/boot/dts/qcom/mdm9607-pinctrl.dtsi +0 −25 Original line number Diff line number Diff line Loading @@ -247,31 +247,6 @@ }; }; i2s_mclk { i2s_mclk_active: i2s_mclk_active { mux { pins = "gpio24"; function = "pri_mi2s_mclk_a"; }; config { pins = "gpio24"; drive-strength = <8>; /* 8 MA */ bias-disable; /* No PULL */ output-high; }; }; i2s_mclk_sleep: i2s_mclk_sleep { mux { pins = "gpio24"; function = "pri_mi2s_mclk_a"; }; config { pins = "gpio24"; drive-strength = <2>; /* 2 MA */ bias-pull-down; /* PULL DOWN */ }; }; }; pmx_pri_mi2s { pri_mi2s_ws_active: pri_mi2s_ws_active { Loading arch/arm/boot/dts/qcom/mdm9607.dtsi +2 −4 Original line number Diff line number Diff line Loading @@ -927,13 +927,11 @@ pinctrl-0 = <&pri_mi2s_ws_active &pri_mi2s_sck_active &pri_mi2s_dout_active &pri_mi2s_din_active &i2s_mclk_active>; &pri_mi2s_din_active>; pinctrl-1 = <&pri_mi2s_ws_sleep &pri_mi2s_sck_sleep &pri_mi2s_dout_sleep &pri_mi2s_din_sleep &i2s_mclk_sleep>; &pri_mi2s_din_sleep>; }; }; Loading Loading
arch/arm/boot/dts/qcom/mdm9607-pinctrl.dtsi +0 −25 Original line number Diff line number Diff line Loading @@ -247,31 +247,6 @@ }; }; i2s_mclk { i2s_mclk_active: i2s_mclk_active { mux { pins = "gpio24"; function = "pri_mi2s_mclk_a"; }; config { pins = "gpio24"; drive-strength = <8>; /* 8 MA */ bias-disable; /* No PULL */ output-high; }; }; i2s_mclk_sleep: i2s_mclk_sleep { mux { pins = "gpio24"; function = "pri_mi2s_mclk_a"; }; config { pins = "gpio24"; drive-strength = <2>; /* 2 MA */ bias-pull-down; /* PULL DOWN */ }; }; }; pmx_pri_mi2s { pri_mi2s_ws_active: pri_mi2s_ws_active { Loading
arch/arm/boot/dts/qcom/mdm9607.dtsi +2 −4 Original line number Diff line number Diff line Loading @@ -927,13 +927,11 @@ pinctrl-0 = <&pri_mi2s_ws_active &pri_mi2s_sck_active &pri_mi2s_dout_active &pri_mi2s_din_active &i2s_mclk_active>; &pri_mi2s_din_active>; pinctrl-1 = <&pri_mi2s_ws_sleep &pri_mi2s_sck_sleep &pri_mi2s_dout_sleep &pri_mi2s_din_sleep &i2s_mclk_sleep>; &pri_mi2s_din_sleep>; }; }; Loading