msm: mdss: fix DSI clock handling for split display configuration

In split display mode, the clocks for both the DSI controllers are
sourced out of a single PLL (typically the left controller). In the
current implementation, the clocks are independently controlled whenever
the broadcast mode is not enabled. However, it is possible that if the
clocks for right controller alone are turned on, the left controller's
phy could already be clamped, leading to that PLL not getting locked.
Fix this issue by ensuring that the clocks for the master controller
(left controller) are always turned on whenever the clocks for the right
controller (or the slave controller) are turned on.

Change-Id: I941865feef44951efe6c55e632938db79e5596ad
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>