Loading Documentation/devicetree/bindings/usb/msm-phy.txt +9 −1 Original line number Diff line number Diff line Loading @@ -138,7 +138,7 @@ Example: QUSB2 High-Speed PHY Required properties: - compatible: Should be "qcom,qusb2phy" - compatible: Should be "qcom,qusb2phy" or "qcom,qusb2phy-v2" - reg: Address and length of the QUSB2 PHY register set - reg-names: Should be "qusb_phy_base". - <supply-name>-supply: phandle to the regulator device tree node Loading @@ -164,16 +164,24 @@ Optional properties: "ref_clk_addr" : ref_clk bcr address used for on/off ref_clk before reset. "tcsr_phy_clk_scheme_sel": address used to determine QUSB PHY clk source. "tcsr_phy_level_shift_keeper": address used to clamp QUSB PHY level shifter. "efuse_addr": EFUSE address to read and update analog tune parameter. - reg-names: Should be "qscratch_base". The qscratch register bank allows us to manipulate QUSB PHY bits eg. to enable D+ pull-up using s/w control in device mode. The reg-names property is required if the reg property is specified. - tcsr_clamp_dig_n" : To enable/disable digital clamp to the phy. When de-asserted, it will prevent random leakage from qusb2 phy resulting from out of sequence turn on/off of 1p8, 3p3 and DVDD regulators. - qcom,qusb-phy-init-seq: QUSB PHY initialization sequence with value,reg pair. - qcom,qusb-phy-host-init-seq: QUSB PHY initialization sequence for host mode with value,reg pair. - qcom,emu-init-seq : emulation initialization sequence with value,reg pair. - qcom,phy-pll-reset-seq : emulation PLL reset sequence with value,reg pair. - qcom,emu-dcm-reset-seq : emulation DCM reset sequence with value,reg pair. - qcom,tune2-efuse-bit-pos: TUNE2 parameter related start bit position with EFUSE register - qcom,tune2-efuse-num-bits: Number of bits based value to use for TUNE2 high nibble - qcom,efuse-bit-pos: start bit position within EFUSE register - qcom,efuse-num-bits: Number of bits to read from EFUSE register - qcom,emulation: Indicates that we are running on emulation platform. - qcom,hold-reset: Indicates that hold QUSB PHY into reset state. - qcom,enable-dpdm-pulsing: enables dp and dm pulsing for PMIC driver to Loading drivers/usb/dwc3/dwc3-msm.c +32 −0 Original line number Diff line number Diff line Loading @@ -1952,6 +1952,36 @@ static void dwc3_msm_bus_vote_w(struct work_struct *w) dev_err(mdwc->dev, "Failed to reset bus bw vote %d\n", ret); } static void dwc3_set_phy_speed_flags(struct dwc3_msm *mdwc) { struct dwc3 *dwc = platform_get_drvdata(mdwc->dwc3); int i, num_ports; u32 reg; mdwc->hs_phy->flags &= ~(PHY_HSFS_MODE | PHY_LS_MODE); if (mdwc->in_host_mode) { reg = dwc3_msm_read_reg(mdwc->base, USB3_HCSPARAMS1); num_ports = HCS_MAX_PORTS(reg); for (i = 0; i < num_ports; i++) { reg = dwc3_msm_read_reg(mdwc->base, USB3_PORTSC + i*0x10); if (reg & PORT_PE) { if (DEV_HIGHSPEED(reg) || DEV_FULLSPEED(reg)) mdwc->hs_phy->flags |= PHY_HSFS_MODE; else if (DEV_LOWSPEED(reg)) mdwc->hs_phy->flags |= PHY_LS_MODE; } } } else { if (dwc->gadget.speed == USB_SPEED_HIGH || dwc->gadget.speed == USB_SPEED_FULL) mdwc->hs_phy->flags |= PHY_HSFS_MODE; else if (dwc->gadget.speed == USB_SPEED_LOW) mdwc->hs_phy->flags |= PHY_LS_MODE; } } static int dwc3_msm_suspend(struct dwc3_msm *mdwc) { int ret, i; Loading Loading @@ -2027,6 +2057,7 @@ static int dwc3_msm_suspend(struct dwc3_msm *mdwc) /* disable power event irq, hs and ss phy irq is used as wake up src */ disable_irq(mdwc->pwr_event_irq); dwc3_set_phy_speed_flags(mdwc); /* Suspend HS PHY */ usb_phy_set_suspend(mdwc->hs_phy, 1); Loading Loading @@ -2168,6 +2199,7 @@ static int dwc3_msm_resume(struct dwc3_msm *mdwc) mdwc->lpm_flags &= ~MDWC3_SS_PHY_SUSPEND; } mdwc->hs_phy->flags &= ~(PHY_HSFS_MODE | PHY_LS_MODE); /* Resume HS PHY */ usb_phy_set_suspend(mdwc->hs_phy, 0); Loading drivers/usb/phy/Makefile +1 −1 Original line number Diff line number Diff line Loading @@ -25,7 +25,7 @@ obj-$(CONFIG_USB_MSM_OTG) += phy-msm-usb.o obj-$(CONFIG_USB_MSM_HSPHY) += phy-msm-hsusb.o obj-$(CONFIG_USB_MSM_SSPHY) += phy-msm-ssusb.o obj-$(CONFIG_USB_MSM_SSPHY_QMP) += phy-msm-ssusb-qmp.o obj-$(CONFIG_MSM_QUSB_PHY) += phy-msm-qusb.o obj-$(CONFIG_MSM_QUSB_PHY) += phy-msm-qusb.o phy-msm-qusb-v2.o obj-$(CONFIG_USB_MV_OTG) += phy-mv-usb.o obj-$(CONFIG_USB_MXS_PHY) += phy-mxs-usb.o obj-$(CONFIG_USB_RCAR_PHY) += phy-rcar-usb.o Loading Loading
Documentation/devicetree/bindings/usb/msm-phy.txt +9 −1 Original line number Diff line number Diff line Loading @@ -138,7 +138,7 @@ Example: QUSB2 High-Speed PHY Required properties: - compatible: Should be "qcom,qusb2phy" - compatible: Should be "qcom,qusb2phy" or "qcom,qusb2phy-v2" - reg: Address and length of the QUSB2 PHY register set - reg-names: Should be "qusb_phy_base". - <supply-name>-supply: phandle to the regulator device tree node Loading @@ -164,16 +164,24 @@ Optional properties: "ref_clk_addr" : ref_clk bcr address used for on/off ref_clk before reset. "tcsr_phy_clk_scheme_sel": address used to determine QUSB PHY clk source. "tcsr_phy_level_shift_keeper": address used to clamp QUSB PHY level shifter. "efuse_addr": EFUSE address to read and update analog tune parameter. - reg-names: Should be "qscratch_base". The qscratch register bank allows us to manipulate QUSB PHY bits eg. to enable D+ pull-up using s/w control in device mode. The reg-names property is required if the reg property is specified. - tcsr_clamp_dig_n" : To enable/disable digital clamp to the phy. When de-asserted, it will prevent random leakage from qusb2 phy resulting from out of sequence turn on/off of 1p8, 3p3 and DVDD regulators. - qcom,qusb-phy-init-seq: QUSB PHY initialization sequence with value,reg pair. - qcom,qusb-phy-host-init-seq: QUSB PHY initialization sequence for host mode with value,reg pair. - qcom,emu-init-seq : emulation initialization sequence with value,reg pair. - qcom,phy-pll-reset-seq : emulation PLL reset sequence with value,reg pair. - qcom,emu-dcm-reset-seq : emulation DCM reset sequence with value,reg pair. - qcom,tune2-efuse-bit-pos: TUNE2 parameter related start bit position with EFUSE register - qcom,tune2-efuse-num-bits: Number of bits based value to use for TUNE2 high nibble - qcom,efuse-bit-pos: start bit position within EFUSE register - qcom,efuse-num-bits: Number of bits to read from EFUSE register - qcom,emulation: Indicates that we are running on emulation platform. - qcom,hold-reset: Indicates that hold QUSB PHY into reset state. - qcom,enable-dpdm-pulsing: enables dp and dm pulsing for PMIC driver to Loading
drivers/usb/dwc3/dwc3-msm.c +32 −0 Original line number Diff line number Diff line Loading @@ -1952,6 +1952,36 @@ static void dwc3_msm_bus_vote_w(struct work_struct *w) dev_err(mdwc->dev, "Failed to reset bus bw vote %d\n", ret); } static void dwc3_set_phy_speed_flags(struct dwc3_msm *mdwc) { struct dwc3 *dwc = platform_get_drvdata(mdwc->dwc3); int i, num_ports; u32 reg; mdwc->hs_phy->flags &= ~(PHY_HSFS_MODE | PHY_LS_MODE); if (mdwc->in_host_mode) { reg = dwc3_msm_read_reg(mdwc->base, USB3_HCSPARAMS1); num_ports = HCS_MAX_PORTS(reg); for (i = 0; i < num_ports; i++) { reg = dwc3_msm_read_reg(mdwc->base, USB3_PORTSC + i*0x10); if (reg & PORT_PE) { if (DEV_HIGHSPEED(reg) || DEV_FULLSPEED(reg)) mdwc->hs_phy->flags |= PHY_HSFS_MODE; else if (DEV_LOWSPEED(reg)) mdwc->hs_phy->flags |= PHY_LS_MODE; } } } else { if (dwc->gadget.speed == USB_SPEED_HIGH || dwc->gadget.speed == USB_SPEED_FULL) mdwc->hs_phy->flags |= PHY_HSFS_MODE; else if (dwc->gadget.speed == USB_SPEED_LOW) mdwc->hs_phy->flags |= PHY_LS_MODE; } } static int dwc3_msm_suspend(struct dwc3_msm *mdwc) { int ret, i; Loading Loading @@ -2027,6 +2057,7 @@ static int dwc3_msm_suspend(struct dwc3_msm *mdwc) /* disable power event irq, hs and ss phy irq is used as wake up src */ disable_irq(mdwc->pwr_event_irq); dwc3_set_phy_speed_flags(mdwc); /* Suspend HS PHY */ usb_phy_set_suspend(mdwc->hs_phy, 1); Loading Loading @@ -2168,6 +2199,7 @@ static int dwc3_msm_resume(struct dwc3_msm *mdwc) mdwc->lpm_flags &= ~MDWC3_SS_PHY_SUSPEND; } mdwc->hs_phy->flags &= ~(PHY_HSFS_MODE | PHY_LS_MODE); /* Resume HS PHY */ usb_phy_set_suspend(mdwc->hs_phy, 0); Loading
drivers/usb/phy/Makefile +1 −1 Original line number Diff line number Diff line Loading @@ -25,7 +25,7 @@ obj-$(CONFIG_USB_MSM_OTG) += phy-msm-usb.o obj-$(CONFIG_USB_MSM_HSPHY) += phy-msm-hsusb.o obj-$(CONFIG_USB_MSM_SSPHY) += phy-msm-ssusb.o obj-$(CONFIG_USB_MSM_SSPHY_QMP) += phy-msm-ssusb-qmp.o obj-$(CONFIG_MSM_QUSB_PHY) += phy-msm-qusb.o obj-$(CONFIG_MSM_QUSB_PHY) += phy-msm-qusb.o phy-msm-qusb-v2.o obj-$(CONFIG_USB_MV_OTG) += phy-mv-usb.o obj-$(CONFIG_USB_MXS_PHY) += phy-mxs-usb.o obj-$(CONFIG_USB_RCAR_PHY) += phy-rcar-usb.o Loading