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Commit bf1e84e8 authored by Mayank Rana's avatar Mayank Rana
Browse files

usb: phy: Add snapshot of USB QUSB PHY v2 driver 



This change adds USB QUSB PHY v2 driver to configure USB QUSB PHY
having major revision version as 2. This snapshot is taken as of
msm-4.4 commit 38c509c5664e ("ARM: dts: msm: Change pinctrl settings
for BLSP1 UART3 for msmcobalt").

It fixes compilation issue by using relevant available API with
msm-3.18 kernel.
1. use msm specific clk_reset() API instead of upstream kernel based
reset clock framework APIs
2. use regulator_set_optimum_mode() API instead of regulator_set_load()
API

CRs-Fixed: 1083141
Change-Id: Iee6b58e9d1b4c6021b33814b3ee3e22b6a8c672e
Signed-off-by: default avatarMayank Rana <mrana@codeaurora.org>
parent 015eb696

Documentation/devicetree/bindings/usb/msm-phy.txt

+9 −1
Original line number Diff line number Diff line
@@ -138,7 +138,7 @@ Example: 
QUSB2 High-Speed PHY



Required properties:

 - compatible: Should be "qcom,qusb2phy"

 - compatible: Should be "qcom,qusb2phy" or "qcom,qusb2phy-v2"

 - reg: Address and length of the QUSB2 PHY register set

 - reg-names: Should be "qusb_phy_base".

 - <supply-name>-supply: phandle to the regulator device tree node
@@ -164,16 +164,24 @@ Optional properties: 
   "ref_clk_addr" : ref_clk bcr address used for on/off ref_clk before reset.

   "tcsr_phy_clk_scheme_sel": address used to determine QUSB PHY clk source.

   "tcsr_phy_level_shift_keeper": address used to clamp QUSB PHY level shifter.

   "efuse_addr": EFUSE address to read and update analog tune parameter.

 - reg-names: Should be "qscratch_base". The qscratch register bank

   allows us to manipulate QUSB PHY bits eg. to enable D+ pull-up using s/w

   control in device mode. The reg-names property is required if the

   reg property is specified.

 - tcsr_clamp_dig_n" : To enable/disable digital clamp to the phy. When

   de-asserted, it will prevent random leakage from qusb2 phy resulting from

   out of sequence turn on/off of 1p8, 3p3 and DVDD regulators.

 - qcom,qusb-phy-init-seq: QUSB PHY initialization sequence with value,reg pair.

 - qcom,qusb-phy-host-init-seq: QUSB PHY initialization sequence for host mode

   with value,reg pair.

 - qcom,emu-init-seq : emulation initialization sequence with value,reg pair.

 - qcom,phy-pll-reset-seq : emulation PLL reset sequence with value,reg pair.

 - qcom,emu-dcm-reset-seq : emulation DCM reset sequence with value,reg pair.

 - qcom,tune2-efuse-bit-pos: TUNE2 parameter related start bit position with EFUSE register

 - qcom,tune2-efuse-num-bits: Number of bits based value to use for TUNE2 high nibble

 - qcom,efuse-bit-pos: start bit position within EFUSE register

 - qcom,efuse-num-bits: Number of bits to read from EFUSE register

 - qcom,emulation: Indicates that we are running on emulation platform.

 - qcom,hold-reset: Indicates that hold QUSB PHY into reset state.

 - qcom,enable-dpdm-pulsing: enables dp and dm pulsing for PMIC driver to

drivers/usb/phy/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -25,7 +25,7 @@ obj-$(CONFIG_USB_MSM_OTG) += phy-msm-usb.o 
obj-$(CONFIG_USB_MSM_HSPHY)     	+= phy-msm-hsusb.o

obj-$(CONFIG_USB_MSM_SSPHY)     	+= phy-msm-ssusb.o

obj-$(CONFIG_USB_MSM_SSPHY_QMP)     	+= phy-msm-ssusb-qmp.o

obj-$(CONFIG_MSM_QUSB_PHY)              += phy-msm-qusb.o

obj-$(CONFIG_MSM_QUSB_PHY)              += phy-msm-qusb.o phy-msm-qusb-v2.o

obj-$(CONFIG_USB_MV_OTG)		+= phy-mv-usb.o

obj-$(CONFIG_USB_MXS_PHY)		+= phy-mxs-usb.o

obj-$(CONFIG_USB_RCAR_PHY)		+= phy-rcar-usb.o

drivers/usb/phy/phy-msm-qusb-v2.c

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