Loading arch/arm/boot/dts/qcom/msm8937-mdss.dtsi +3 −3 Original line number Diff line number Diff line Loading @@ -89,7 +89,7 @@ clocks = <&clock_gcc clk_gcc_mdss_ahb_clk>, <&clock_gcc clk_gcc_mdss_axi_clk>, <&clock_gcc clk_mdp_clk_src>, <&clock_gcc clk_gcc_mdss_mdp_clk>, <&clock_gcc_mdss clk_mdss_mdp_vote_clk>, <&clock_gcc clk_gcc_mdss_vsync_clk>; clock-names = "iface_clk", "bus_clk", "core_clk_src", "core_clk", "vsync_clk"; Loading Loading @@ -205,7 +205,7 @@ 0x1a96b80 0x1a96b80 0x30 0x193e000 0x193e000 0x30>; clocks = <&clock_gcc clk_gcc_mdss_mdp_clk>, clocks = <&clock_gcc_mdss clk_mdss_mdp_vote_clk>, <&clock_gcc clk_gcc_mdss_ahb_clk>, <&clock_gcc clk_gcc_mdss_axi_clk>, <&clock_gcc_mdss clk_ext_byte0_clk_src>, Loading Loading @@ -361,7 +361,7 @@ qcom,supply-names = "rot-vdd"; clocks = <&clock_gcc clk_gcc_mdss_ahb_clk>, <&clock_gcc clk_gcc_mdss_mdp_clk>; <&clock_gcc_mdss clk_mdss_rotator_vote_clk>; clock-names = "iface_clk", "rot_core_clk"; }; Loading drivers/clk/msm/clock-gcc-8952.c +5 −0 Original line number Diff line number Diff line Loading @@ -2673,6 +2673,9 @@ static struct branch_clk gcc_mdss_mdp_clk = { }, }; static DEFINE_CLK_VOTER(mdss_mdp_vote_clk, &gcc_mdss_mdp_clk.c, 0); static DEFINE_CLK_VOTER(mdss_rotator_vote_clk, &gcc_mdss_mdp_clk.c, 0); static struct branch_clk gcc_mdss_pclk0_clk = { .cbcr_reg = MDSS_PCLK0_CBCR, .has_sibling = 0, Loading Loading @@ -4258,6 +4261,8 @@ static struct clk_lookup msm_clocks_gcc_mdss_8937[] = { CLK_LIST(ext_byte1_clk_src), CLK_LIST(gcc_mdss_pclk1_clk), CLK_LIST(gcc_mdss_byte1_clk), CLK_LIST(mdss_mdp_vote_clk), CLK_LIST(mdss_rotator_vote_clk), }; static int msm_gcc_mdss_probe(struct platform_device *pdev) Loading include/dt-bindings/clock/msm-clocks-8952.h +2 −0 Original line number Diff line number Diff line Loading @@ -225,6 +225,8 @@ #define clk_gcc_bimc_gfx_clk 0x3edd69ad #define clk_ipa_clk 0xfa685cda #define clk_ipa_a_clk 0xeeec2919 #define clk_mdss_mdp_vote_clk 0x588460a4 #define clk_mdss_rotator_vote_clk 0x5b1f675e #define clk_pixel_clk_src 0x8b6f83d8 #define clk_byte_clk_src 0x3a911c53 Loading Loading
arch/arm/boot/dts/qcom/msm8937-mdss.dtsi +3 −3 Original line number Diff line number Diff line Loading @@ -89,7 +89,7 @@ clocks = <&clock_gcc clk_gcc_mdss_ahb_clk>, <&clock_gcc clk_gcc_mdss_axi_clk>, <&clock_gcc clk_mdp_clk_src>, <&clock_gcc clk_gcc_mdss_mdp_clk>, <&clock_gcc_mdss clk_mdss_mdp_vote_clk>, <&clock_gcc clk_gcc_mdss_vsync_clk>; clock-names = "iface_clk", "bus_clk", "core_clk_src", "core_clk", "vsync_clk"; Loading Loading @@ -205,7 +205,7 @@ 0x1a96b80 0x1a96b80 0x30 0x193e000 0x193e000 0x30>; clocks = <&clock_gcc clk_gcc_mdss_mdp_clk>, clocks = <&clock_gcc_mdss clk_mdss_mdp_vote_clk>, <&clock_gcc clk_gcc_mdss_ahb_clk>, <&clock_gcc clk_gcc_mdss_axi_clk>, <&clock_gcc_mdss clk_ext_byte0_clk_src>, Loading Loading @@ -361,7 +361,7 @@ qcom,supply-names = "rot-vdd"; clocks = <&clock_gcc clk_gcc_mdss_ahb_clk>, <&clock_gcc clk_gcc_mdss_mdp_clk>; <&clock_gcc_mdss clk_mdss_rotator_vote_clk>; clock-names = "iface_clk", "rot_core_clk"; }; Loading
drivers/clk/msm/clock-gcc-8952.c +5 −0 Original line number Diff line number Diff line Loading @@ -2673,6 +2673,9 @@ static struct branch_clk gcc_mdss_mdp_clk = { }, }; static DEFINE_CLK_VOTER(mdss_mdp_vote_clk, &gcc_mdss_mdp_clk.c, 0); static DEFINE_CLK_VOTER(mdss_rotator_vote_clk, &gcc_mdss_mdp_clk.c, 0); static struct branch_clk gcc_mdss_pclk0_clk = { .cbcr_reg = MDSS_PCLK0_CBCR, .has_sibling = 0, Loading Loading @@ -4258,6 +4261,8 @@ static struct clk_lookup msm_clocks_gcc_mdss_8937[] = { CLK_LIST(ext_byte1_clk_src), CLK_LIST(gcc_mdss_pclk1_clk), CLK_LIST(gcc_mdss_byte1_clk), CLK_LIST(mdss_mdp_vote_clk), CLK_LIST(mdss_rotator_vote_clk), }; static int msm_gcc_mdss_probe(struct platform_device *pdev) Loading
include/dt-bindings/clock/msm-clocks-8952.h +2 −0 Original line number Diff line number Diff line Loading @@ -225,6 +225,8 @@ #define clk_gcc_bimc_gfx_clk 0x3edd69ad #define clk_ipa_clk 0xfa685cda #define clk_ipa_a_clk 0xeeec2919 #define clk_mdss_mdp_vote_clk 0x588460a4 #define clk_mdss_rotator_vote_clk 0x5b1f675e #define clk_pixel_clk_src 0x8b6f83d8 #define clk_byte_clk_src 0x3a911c53 Loading