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Commit 14519296 authored by Deepak Katragadda's avatar Deepak Katragadda Committed by Devesh Jhunjhunwala
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ARM: dts: msm: Add the timeout properties to SMMU GDSCs on MSM8996 



The votable SMMU GDSCs might take longer to enable than the
default limit of 100usecs depending on the clock WAKE and SLEEP
settings and the clock rates. Make this polling timeout limit
more configurable.

Change-Id: I26cb00cefa5d45ed2a92f306921e2d95938795af
Signed-off-by: default avatarDeepak Katragadda <dkatraga@codeaurora.org>
parent 61691972

Documentation/devicetree/bindings/regulator/gdsc-regulator.txt

+2 −0
Original line number Original line Diff line number Diff line
@@ -46,6 +46,8 @@ Optional properties: 
 - qcom,disallow-clear: Presence denotes the periph & core memory will not be

 - qcom,disallow-clear: Presence denotes the periph & core memory will not be

			cleared, unless the required subsystem does not invoke

			cleared, unless the required subsystem does not invoke

			the api which will allow clearing the bits.

			the api which will allow clearing the bits.

 - qcom,gds-timeout:	Maximum time (in usecs) that might be taken by a GDSC

			to enable.





Example:

Example:

	gdsc_oxili_gx: qcom,gdsc@fd8c4024 {

	gdsc_oxili_gx: qcom,gdsc@fd8c4024 {

arch/arm/boot/dts/qcom/msm-gdsc-8996.dtsi

+5 −0
Original line number Original line Diff line number Diff line
@@ -26,6 +26,7 @@ 
		      <0x8c120c 0x4>;

		      <0x8c120c 0x4>;

		reg-names = "base", "hw_ctrl_addr";

		reg-names = "base", "hw_ctrl_addr";

		qcom,no-status-check-on-disable;

		qcom,no-status-check-on-disable;

		qcom,gds-timeout = <500>;

		status = "disabled";

		status = "disabled";

	};

	};
@@ -36,6 +37,7 @@ 
		      <0x8c2480 0x4>;

		      <0x8c2480 0x4>;

		reg-names = "base", "hw_ctrl_addr";

		reg-names = "base", "hw_ctrl_addr";

		qcom,no-status-check-on-disable;

		qcom,no-status-check-on-disable;

		qcom,gds-timeout = <500>;

		status = "disabled";

		status = "disabled";

	};

	};
@@ -46,6 +48,7 @@ 
		      <0x8c3c50 0x4>;

		      <0x8c3c50 0x4>;

		reg-names = "base", "hw_ctrl_addr";

		reg-names = "base", "hw_ctrl_addr";

		qcom,no-status-check-on-disable;

		qcom,no-status-check-on-disable;

		qcom,gds-timeout = <500>;

		status = "disabled";

		status = "disabled";

	};

	};
@@ -161,6 +164,7 @@ 
		      <0x8c4038 0x4>;

		      <0x8c4038 0x4>;

		reg-names = "base", "hw_ctrl_addr";

		reg-names = "base", "hw_ctrl_addr";

		qcom,no-status-check-on-disable;

		qcom,no-status-check-on-disable;

		qcom,gds-timeout = <500>;

		status = "disabled";

		status = "disabled";

	};

	};
@@ -204,6 +208,7 @@ 
		      <0x381028 0x4>;

		      <0x381028 0x4>;

		reg-names = "base", "hw_ctrl_addr";

		reg-names = "base", "hw_ctrl_addr";

		qcom,no-status-check-on-disable;

		qcom,no-status-check-on-disable;

		qcom,gds-timeout = <500>;

		status = "disabled";

		status = "disabled";

	};

	};

};
 
};