Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 1411e6a5 authored by Kenneth Graunke's avatar Kenneth Graunke Committed by Daniel Vetter
Browse files

drm/i915: Add thread stall DOP clock gating workaround on Broadwell. 



Ben and I believe this will be necessary on production hardware.

Signed-off-by: default avatarKenneth Graunke <kenneth@whitecape.org>
[danvet: Shuffle lines to group all ROW_CHICKEN writes and add a
cautious comment that this might not be needed on production hw.]
Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: default avatarBen Widawsky <ben@bwidawsk.net>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent c8966e10

drivers/gpu/drm/i915/i915_reg.h

+1 −0
Original line number Diff line number Diff line
@@ -5050,6 +5050,7 @@ 


#define GEN8_ROW_CHICKEN		0xe4f0

#define   PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE	(1<<8)

#define   STALL_DOP_GATING_DISABLE		(1<<5)



#define GEN7_ROW_CHICKEN2		0xe4f4

#define GEN7_ROW_CHICKEN2_GT2		0xf4f4

drivers/gpu/drm/i915/intel_pm.c

+5 −0
Original line number Diff line number Diff line
@@ -4805,6 +4805,11 @@ static void gen8_init_clock_gating(struct drm_device *dev) 
	I915_WRITE(GEN8_ROW_CHICKEN,

		   _MASKED_BIT_ENABLE(PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE));



	/* WaDisableThreadStallDopClockGating:bdw */

	/* FIXME: Unclear whether we really need this on production bdw. */

	I915_WRITE(GEN8_ROW_CHICKEN,

		   _MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE));



	/*

	 * This GEN8_CENTROID_PIXEL_OPT_DIS W/A is only needed for

	 * pre-production hardware