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Commit 13b3d13b authored by Michael Ellerman's avatar Michael Ellerman Committed by Benjamin Herrenschmidt
Browse files

powerpc: Remove MMU_FTR_SLB 



We now only support cpus that use an SLB, so we don't need an MMU
feature to indicate that.

Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
Signed-off-by: default avatarBenjamin Herrenschmidt <benh@kernel.crashing.org>
parent 376af594

arch/powerpc/include/asm/cputable.h

+1 −2
Original line number Diff line number Diff line
@@ -195,8 +195,7 @@ extern const char *powerpc_base_platform; 


#define CPU_FTR_PPCAS_ARCH_V2	(CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN)



#define MMU_FTR_PPCAS_ARCH_V2 	(MMU_FTR_SLB | MMU_FTR_TLBIEL | \

				 MMU_FTR_16M_PAGE)

#define MMU_FTR_PPCAS_ARCH_V2 	(MMU_FTR_TLBIEL | MMU_FTR_16M_PAGE)



/* We only set the altivec features if the kernel was compiled with altivec

 * support

arch/powerpc/include/asm/mmu.h

+2 −6
Original line number Diff line number Diff line
@@ -64,9 +64,9 @@ 
 */

#define MMU_FTR_USE_PAIRED_MAS		ASM_CONST(0x01000000)



/* MMU is SLB-based

/* Doesn't support the B bit (1T segment) in SLBIE

 */

#define MMU_FTR_SLB			ASM_CONST(0x02000000)

#define MMU_FTR_NO_SLBIE_B		ASM_CONST(0x02000000)



/* Support 16M large pages

 */
@@ -88,10 +88,6 @@ 
 */

#define MMU_FTR_1T_SEGMENT		ASM_CONST(0x40000000)



/* Doesn't support the B bit (1T segment) in SLBIE

 */

#define MMU_FTR_NO_SLBIE_B		ASM_CONST(0x80000000)



/* MMU feature bit sets for various CPUs */

#define MMU_FTRS_DEFAULT_HPTE_ARCH_V2	\

	MMU_FTR_HPTE_TABLE | MMU_FTR_PPCAS_ARCH_V2

arch/powerpc/include/asm/mmu_context.h

+1 −2
Original line number Diff line number Diff line
@@ -76,7 +76,6 @@ static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, 
	 * sub architectures.

	 */

#ifdef CONFIG_PPC_STD_MMU_64

	if (mmu_has_feature(MMU_FTR_SLB))

	switch_slb(tsk, next);

#else

	/* Out of line for now */

arch/powerpc/kernel/entry_64.S

+2 −6
Original line number Diff line number Diff line
@@ -482,16 +482,12 @@ END_FTR_SECTION_IFSET(CPU_FTR_STCX_CHECKS_ADDRESS) 
	ld	r8,KSP(r4)	/* new stack pointer */

#ifdef CONFIG_PPC_BOOK3S

BEGIN_FTR_SECTION

  BEGIN_FTR_SECTION_NESTED(95)

	clrrdi	r6,r8,28	/* get its ESID */

	clrrdi	r9,r1,28	/* get current sp ESID */

  FTR_SECTION_ELSE_NESTED(95)

FTR_SECTION_ELSE

	clrrdi	r6,r8,40	/* get its 1T ESID */

	clrrdi	r9,r1,40	/* get current sp 1T ESID */

  ALT_MMU_FTR_SECTION_END_NESTED_IFCLR(MMU_FTR_1T_SEGMENT, 95)

FTR_SECTION_ELSE

	b	2f

ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_SLB)

ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_1T_SEGMENT)

	clrldi.	r0,r6,2		/* is new ESID c00000000? */

	cmpd	cr1,r6,r9	/* or is new ESID the same as current ESID? */

	cror	eq,4*cr1+eq,eq

arch/powerpc/kernel/process.c

+1 −1
Original line number Diff line number Diff line
@@ -1175,7 +1175,7 @@ int copy_thread(unsigned long clone_flags, unsigned long usp, 
#endif



#ifdef CONFIG_PPC_STD_MMU_64

	if (mmu_has_feature(MMU_FTR_SLB)) {

	{

		unsigned long sp_vsid;

		unsigned long llp = mmu_psize_defs[mmu_linear_psize].sllp;