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Commit 376af594 authored by Michael Ellerman's avatar Michael Ellerman Committed by Benjamin Herrenschmidt
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powerpc: Remove STAB code 



Old cpus didn't have a Segment Lookaside Buffer (SLB), instead they had
a Segment Table (STAB). Now that we've dropped support for those cpus,
we can remove the STAB support entirely.

Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
Signed-off-by: default avatarBenjamin Herrenschmidt <benh@kernel.crashing.org>
parent 468a3302

arch/powerpc/include/asm/mmu-hash64.h

+0 −22
Original line number Diff line number Diff line
@@ -24,26 +24,6 @@ 
#include <asm/bug.h>

#include <asm/processor.h>



/*

 * Segment table

 */



#define STE_ESID_V	0x80

#define STE_ESID_KS	0x20

#define STE_ESID_KP	0x10

#define STE_ESID_N	0x08



#define STE_VSID_SHIFT	12



/* Location of cpu0's segment table */

#define STAB0_PAGE	0x8

#define STAB0_OFFSET	(STAB0_PAGE << 12)

#define STAB0_PHYS_ADDR	(STAB0_OFFSET + PHYSICAL_START)



#ifndef __ASSEMBLY__

extern char initial_stab[];

#endif /* ! __ASSEMBLY */



/*

 * SLB

 */
@@ -370,10 +350,8 @@ extern void hpte_init_lpar(void); 
extern void hpte_init_beat(void);

extern void hpte_init_beat_v3(void);



extern void stabs_alloc(void);

extern void slb_initialize(void);

extern void slb_flush_and_rebolt(void);

extern void stab_initialize(unsigned long stab);



extern void slb_vmalloc_update(void);

extern void slb_set_size(u16 size);

arch/powerpc/include/asm/mmu_context.h

+0 −3
Original line number Diff line number Diff line
@@ -18,7 +18,6 @@ extern int init_new_context(struct task_struct *tsk, struct mm_struct *mm); 
extern void destroy_context(struct mm_struct *mm);



extern void switch_mmu_context(struct mm_struct *prev, struct mm_struct *next);

extern void switch_stab(struct task_struct *tsk, struct mm_struct *mm);

extern void switch_slb(struct task_struct *tsk, struct mm_struct *mm);

extern void set_context(unsigned long id, pgd_t *pgd);
@@ -79,8 +78,6 @@ static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, 
#ifdef CONFIG_PPC_STD_MMU_64

	if (mmu_has_feature(MMU_FTR_SLB))

		switch_slb(tsk, next);

	else

		switch_stab(tsk, next);

#else

	/* Out of line for now */

	switch_mmu_context(prev, next);

arch/powerpc/include/asm/paca.h

+0 −4
Original line number Diff line number Diff line
@@ -78,10 +78,6 @@ struct paca_struct { 
	u64 kernel_toc;			/* Kernel TOC address */

	u64 kernelbase;			/* Base address of kernel */

	u64 kernel_msr;			/* MSR while running in kernel */

#ifdef CONFIG_PPC_STD_MMU_64

	u64 stab_real;			/* Absolute address of segment table */

	u64 stab_addr;			/* Virtual address of segment table */

#endif /* CONFIG_PPC_STD_MMU_64 */

	void *emergency_sp;		/* pointer to emergency stack */

	u64 data_offset;		/* per cpu data offset */

	s16 hw_cpu_id;			/* Physical processor number */

arch/powerpc/include/asm/reg.h

+1 −1
Original line number Diff line number Diff line
@@ -254,7 +254,7 @@ 
#define   DSISR_PROTFAULT	0x08000000	/* protection fault */

#define   DSISR_ISSTORE		0x02000000	/* access was a store */

#define   DSISR_DABRMATCH	0x00400000	/* hit data breakpoint */

#define   DSISR_NOSEGMENT	0x00200000	/* STAB/SLB miss */

#define   DSISR_NOSEGMENT	0x00200000	/* SLB miss */

#define   DSISR_KEYFAULT	0x00200000	/* Key fault */

#define SPRN_TBRL	0x10C	/* Time Base Read Lower Register (user, R/O) */

#define SPRN_TBRU	0x10D	/* Time Base Read Upper Register (user, R/O) */

arch/powerpc/kernel/asm-offsets.c

+0 −2
Original line number Diff line number Diff line
@@ -216,8 +216,6 @@ int main(void) 
#endif /* CONFIG_PPC_BOOK3E */



#ifdef CONFIG_PPC_STD_MMU_64

	DEFINE(PACASTABREAL, offsetof(struct paca_struct, stab_real));

	DEFINE(PACASTABVIRT, offsetof(struct paca_struct, stab_addr));

	DEFINE(PACASLBCACHE, offsetof(struct paca_struct, slb_cache));

	DEFINE(PACASLBCACHEPTR, offsetof(struct paca_struct, slb_cache_ptr));

	DEFINE(PACAVMALLOCSLLP, offsetof(struct paca_struct, vmalloc_sllp));