Loading arch/arm/boot/dts/qcom/msmgold-regulator.dtsi +3 −4 Original line number Diff line number Diff line Loading @@ -355,7 +355,7 @@ interrupts = <0 15 0>; regulator-name = "apc_corner"; regulator-min-microvolt = <1>; regulator-max-microvolt = <4>; regulator-max-microvolt = <3>; qcom,cpr-fuse-corners = <3>; qcom,cpr-voltage-ceiling = <1155000 1225000 1350000>; Loading Loading @@ -392,12 +392,11 @@ <70 54 7 0>; qcom,cpr-fuse-quot-offset-scale = <5 5 5>; qcom,cpr-init-voltage-step = <10000>; qcom,cpr-corner-map = <1 2 3 3>; qcom,cpr-corner-map = <1 2 3>; qcom,cpr-corner-frequency-map = <1 998400000>, <2 1094400000>, <3 1248000000>, <4 1401000000>; <3 1209600000>; qcom,speed-bin-fuse-sel = <37 34 3 0>; qcom,cpr-quot-adjust-scaling-factor-max = <0 1400 1400>; qcom,cpr-fuse-revision = <69 39 3 0>; Loading arch/arm/boot/dts/qcom/msmgold.dtsi +2 −4 Original line number Diff line number Diff line Loading @@ -465,8 +465,7 @@ < 0 0>, < 998400000 1>, < 1094400000 2>, < 1248000000 3>, < 1401000000 4>; < 1209600000 3>; #clock-cells = <1>; }; Loading @@ -483,8 +482,7 @@ qcom,cpufreq-table-0 = < 998400 >, < 1094400 >, < 1248000 >, < 1401000 >; < 1209600 >; }; qcom,wdt@b017000 { Loading drivers/clk/msm/clock-gcc-8952.c +1 −0 Original line number Diff line number Diff line Loading @@ -241,6 +241,7 @@ static struct pll_freq_tbl apcs_c1_pll_freq[] = { F_APCS_PLL(1094400000, 57, 0x0, 0x1, 0x0, 0x0, 0x0), F_APCS_PLL(1113600000, 58, 0x0, 0x1, 0x0, 0x0, 0x0), F_APCS_PLL(1190400000, 62, 0x0, 0x1, 0x0, 0x0, 0x0), F_APCS_PLL(1209600000, 63, 0x0, 0x1, 0x0, 0x0, 0x0), F_APCS_PLL(1248000000, 65, 0x0, 0x1, 0x0, 0x0, 0x0), F_APCS_PLL(1267200000, 66, 0x0, 0x1, 0x0, 0x0, 0x0), F_APCS_PLL(1344000000, 70, 0x0, 0x1, 0x0, 0x0, 0x0), Loading Loading
arch/arm/boot/dts/qcom/msmgold-regulator.dtsi +3 −4 Original line number Diff line number Diff line Loading @@ -355,7 +355,7 @@ interrupts = <0 15 0>; regulator-name = "apc_corner"; regulator-min-microvolt = <1>; regulator-max-microvolt = <4>; regulator-max-microvolt = <3>; qcom,cpr-fuse-corners = <3>; qcom,cpr-voltage-ceiling = <1155000 1225000 1350000>; Loading Loading @@ -392,12 +392,11 @@ <70 54 7 0>; qcom,cpr-fuse-quot-offset-scale = <5 5 5>; qcom,cpr-init-voltage-step = <10000>; qcom,cpr-corner-map = <1 2 3 3>; qcom,cpr-corner-map = <1 2 3>; qcom,cpr-corner-frequency-map = <1 998400000>, <2 1094400000>, <3 1248000000>, <4 1401000000>; <3 1209600000>; qcom,speed-bin-fuse-sel = <37 34 3 0>; qcom,cpr-quot-adjust-scaling-factor-max = <0 1400 1400>; qcom,cpr-fuse-revision = <69 39 3 0>; Loading
arch/arm/boot/dts/qcom/msmgold.dtsi +2 −4 Original line number Diff line number Diff line Loading @@ -465,8 +465,7 @@ < 0 0>, < 998400000 1>, < 1094400000 2>, < 1248000000 3>, < 1401000000 4>; < 1209600000 3>; #clock-cells = <1>; }; Loading @@ -483,8 +482,7 @@ qcom,cpufreq-table-0 = < 998400 >, < 1094400 >, < 1248000 >, < 1401000 >; < 1209600 >; }; qcom,wdt@b017000 { Loading
drivers/clk/msm/clock-gcc-8952.c +1 −0 Original line number Diff line number Diff line Loading @@ -241,6 +241,7 @@ static struct pll_freq_tbl apcs_c1_pll_freq[] = { F_APCS_PLL(1094400000, 57, 0x0, 0x1, 0x0, 0x0, 0x0), F_APCS_PLL(1113600000, 58, 0x0, 0x1, 0x0, 0x0, 0x0), F_APCS_PLL(1190400000, 62, 0x0, 0x1, 0x0, 0x0, 0x0), F_APCS_PLL(1209600000, 63, 0x0, 0x1, 0x0, 0x0, 0x0), F_APCS_PLL(1248000000, 65, 0x0, 0x1, 0x0, 0x0, 0x0), F_APCS_PLL(1267200000, 66, 0x0, 0x1, 0x0, 0x0, 0x0), F_APCS_PLL(1344000000, 70, 0x0, 0x1, 0x0, 0x0, 0x0), Loading