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Commit a635d1a6 authored by Taniya Das's avatar Taniya Das
Browse files

ARM: dts: msm: Limit CPU clock fmax for MSMGold 



MSMgold Fmax is updated to support 1.2GHz, so lower the fmax and also
update the frequency table and the CPR node to reflect the same.

Change-Id: I866ec5a98fb4c0bc56fbb2b8560ea4ed86d8e7a5
Signed-off-by: default avatarTaniya Das <tdas@codeaurora.org>
parent 5c8f9e96

arch/arm/boot/dts/qcom/msmgold-regulator.dtsi

+3 −4
Original line number Diff line number Diff line
@@ -355,7 +355,7 @@ 
		interrupts = <0 15 0>;

		regulator-name = "apc_corner";

		regulator-min-microvolt = <1>;

		regulator-max-microvolt = <4>;

		regulator-max-microvolt = <3>;



		qcom,cpr-fuse-corners = <3>;

		qcom,cpr-voltage-ceiling = <1155000 1225000 1350000>;
@@ -392,12 +392,11 @@ 
					<70 54 7 0>;

		qcom,cpr-fuse-quot-offset-scale = <5 5 5>;

		qcom,cpr-init-voltage-step = <10000>;

		qcom,cpr-corner-map = <1 2 3 3>;

		qcom,cpr-corner-map = <1 2 3>;

		qcom,cpr-corner-frequency-map =

				<1 998400000>,

				<2 1094400000>,

				<3 1248000000>,

				<4 1401000000>;

				<3 1209600000>;

		qcom,speed-bin-fuse-sel = <37 34 3 0>;

		qcom,cpr-quot-adjust-scaling-factor-max = <0 1400 1400>;

		qcom,cpr-fuse-revision = <69 39 3 0>;

arch/arm/boot/dts/qcom/msmgold.dtsi

+2 −4
Original line number Diff line number Diff line
@@ -457,8 +457,7 @@ 
			<          0 0>,

			<  998400000 1>,

			< 1094400000 2>,

			< 1248000000 3>,

			< 1401000000 4>;

			< 1209600000 3>;



		#clock-cells = <1>;

	};
@@ -475,8 +474,7 @@ 
		qcom,cpufreq-table-0 =

			 <  998400 >,

			 < 1094400 >,

			 < 1248000 >,

			 < 1401000 >;

			 < 1209600 >;

	};



	qcom,wdt@b017000 {

drivers/clk/msm/clock-gcc-8952.c

+1 −0
Original line number Diff line number Diff line
@@ -241,6 +241,7 @@ static struct pll_freq_tbl apcs_c1_pll_freq[] = { 
	F_APCS_PLL(1094400000, 57, 0x0, 0x1, 0x0, 0x0, 0x0),

	F_APCS_PLL(1113600000, 58, 0x0, 0x1, 0x0, 0x0, 0x0),

	F_APCS_PLL(1190400000, 62, 0x0, 0x1, 0x0, 0x0, 0x0),

	F_APCS_PLL(1209600000, 63, 0x0, 0x1, 0x0, 0x0, 0x0),

	F_APCS_PLL(1248000000, 65, 0x0, 0x1, 0x0, 0x0, 0x0),

	F_APCS_PLL(1267200000, 66, 0x0, 0x1, 0x0, 0x0, 0x0),

	F_APCS_PLL(1344000000, 70, 0x0, 0x1, 0x0, 0x0, 0x0),