Loading arch/arm/boot/dts/qcom/apq8017-no-pmi-wcd-rome-cdp.dts +2 −2 Original line number Diff line number Diff line Loading @@ -114,8 +114,8 @@ qcom,lpass-mclk-id = "sec_mclk"; qcom,codec-mclk-clk-freq = <12288000>; pinctrl-names = "sleep", "active"; pinctrl-0 = <&sec_mi2s_mclk_a_sleep>; pinctrl-1 = <&sec_mi2s_mclk_a_active>; pinctrl-0 = <&pri_mi2s_mclk_b_default &sec_mi2s_mclk_a_sleep>; pinctrl-1 = <&pri_mi2s_mclk_b_default &sec_mi2s_mclk_a_active>; }; }; Loading arch/arm/boot/dts/qcom/msm8917-pinctrl.dtsi +15 −0 Original line number Diff line number Diff line Loading @@ -722,6 +722,21 @@ }; }; pri_mi2s_mclk_b_lines { pri_mi2s_mclk_b_default: pri_mi2s_mclk_default { mux { pins = "gpio69"; function = "pri_mi2s_mclk_b"; }; config { pins = "gpio69"; drive-strength = <8>; bias-disable; input-enable; }; }; }; sec_mi2s_mclk_a_lines { sec_mi2s_mclk_a_active: sec_mi2s_mclk_a_active { mux { Loading Loading
arch/arm/boot/dts/qcom/apq8017-no-pmi-wcd-rome-cdp.dts +2 −2 Original line number Diff line number Diff line Loading @@ -114,8 +114,8 @@ qcom,lpass-mclk-id = "sec_mclk"; qcom,codec-mclk-clk-freq = <12288000>; pinctrl-names = "sleep", "active"; pinctrl-0 = <&sec_mi2s_mclk_a_sleep>; pinctrl-1 = <&sec_mi2s_mclk_a_active>; pinctrl-0 = <&pri_mi2s_mclk_b_default &sec_mi2s_mclk_a_sleep>; pinctrl-1 = <&pri_mi2s_mclk_b_default &sec_mi2s_mclk_a_active>; }; }; Loading
arch/arm/boot/dts/qcom/msm8917-pinctrl.dtsi +15 −0 Original line number Diff line number Diff line Loading @@ -722,6 +722,21 @@ }; }; pri_mi2s_mclk_b_lines { pri_mi2s_mclk_b_default: pri_mi2s_mclk_default { mux { pins = "gpio69"; function = "pri_mi2s_mclk_b"; }; config { pins = "gpio69"; drive-strength = <8>; bias-disable; input-enable; }; }; }; sec_mi2s_mclk_a_lines { sec_mi2s_mclk_a_active: sec_mi2s_mclk_a_active { mux { Loading