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Commit 0ef16239 authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: Add GPU mempools properties for all msm"

parents a6b8f051 f37c8c2d

Documentation/devicetree/bindings/gpu/adreno.txt

+51 −0
Original line number Diff line number Diff line
@@ -164,6 +164,23 @@ GPU Quirks: 
- qcom,gpu-quirk-dp2clockgating-disable:

				Disable RB sampler data path clock gating optimization



KGSL Memory Pools:

- qcom,gpu-mempools:		Container for sets of GPU mempools.Multiple sets

				(pools) can be defined within qcom,gpu-mempools.

				Each mempool defines a pool order, reserved pages,

				allocation allowed.

Properties:

- compatible:			Must be qcom,gpu-mempools.

- qcom,mempool-max-pages:	Max pages for all mempools, If not defined there is no limit.

- qcom,gpu-mempool:		Defines a set of mempools.



Properties:

- reg:				Index of the pool (0 = lowest pool order).

- qcom,mempool-page-size:	Size of page.

- qcom,mempool-reserved:	Number of pages reserved at init time for a pool.

- qcom,mempool-allocate:	Allocate memory from the system memory when the

				reserved pool exhausted.



The following properties are optional as collecting data via coresight might

not be supported for every chipset. The documentation for coresight

properties can be found in:
@@ -240,6 +257,40 @@ Example of A330 GPU in MSM8916: 
		/* Context aware jump target power level */

		qcom,ca-target-pwrlevel = <1>;



		/* GPU Mempools */

		qcom,gpu-mempools {

			#address-cells= <1>;

			#size-cells = <0>;

			compatible = "qcom,gpu-mempools";



			/* 4K Page Pool configuration */

			qcom,gpu-mempool@0 {

				reg = <0>;

				qcom,mempool-page-size = <4096>;

				qcom,mempool-reserved = <2048>;

				qcom,mempool-allocate;

			};

			/* 8K Page Pool configuration */

			qcom,gpu-mempool@1 {

				reg = <1>;

				qcom,mempool-page-size  = <8192>;

				qcom,mempool-reserved = <1024>;

				qcom,mempool-allocate;

			};

			/* 64K Page Pool configuration */

			qcom,gpu-mempool@2 {

				reg = <2>;

				qcom,mempool-page-size  = <65536>;

				qcom,mempool-reserved = <256>;

			};

			/* 1M Page Pool configuration */

			qcom,gpu-mempool@3 {

				reg = <3>;

				qcom,mempool-page-size  = <1048576>;

				qcom,mempool-reserved = <32>;

			};

		};



		/* Power levels */

		qcom,gpu-pwrlevels-bins {

			#address-cells = <1>;

arch/arm/boot/dts/qcom/msm8909-gpu.dtsi

+20 −0
Original line number Diff line number Diff line
@@ -95,6 +95,26 @@ 
		qcom,pm-qos-active-latency = <701>;

		qcom,pm-qos-wakeup-latency = <701>;



		/* GPU Mempools */

		qcom,gpu-mempools {

			#address-cells= <1>;

			#size-cells = <0>;

			compatible = "qcom,gpu-mempools";



			qcom,mempool-max-pages = <32768>;



			/* 4K Page Pool configuration */

			qcom,gpu-mempool@0 {

				reg = <0>;

				qcom,mempool-page-size = <4096>;

			};

			/* 64K Page Pool configuration */

			qcom,gpu-mempool@1 {

				reg = <1>;

				qcom,mempool-page-size  = <65536>;

			};

		};



		/* Power levels */

		qcom,gpu-pwrlevels {

			#address-cells = <1>;

arch/arm/boot/dts/qcom/msm8917-gpu.dtsi

+20 −0
Original line number Diff line number Diff line
@@ -109,6 +109,26 @@ 
		coresight-child-list = <&funnel_mm>;

		coresight-child-ports = <6>;



		/* GPU Mempools */

		qcom,gpu-mempools {

			#address-cells= <1>;

			#size-cells = <0>;

			compatible = "qcom,gpu-mempools";



			qcom,mempool-max-pages = <32768>;



			/* 4K Page Pool configuration */

			qcom,gpu-mempool@0 {

				reg = <0>;

				qcom,mempool-page-size = <4096>;

			};

			/* 64K Page Pool configuration */

			qcom,gpu-mempool@1 {

				reg = <1>;

				qcom,mempool-page-size  = <65536>;

			};

		};



		/* Power levels */

		qcom,gpu-pwrlevels {

			#address-cells = <1>;

arch/arm/boot/dts/qcom/msm8937-gpu.dtsi

+20 −0
Original line number Diff line number Diff line
@@ -124,6 +124,26 @@ 
		/* Context aware jump target power level */

		qcom,ca-target-pwrlevel = <1>;



		/* GPU Mempools */

		qcom,gpu-mempools {

			#address-cells= <1>;

			#size-cells = <0>;

			compatible = "qcom,gpu-mempools";



			qcom,mempool-max-pages = <32768>;



			/* 4K Page Pool configuration */

			qcom,gpu-mempool@0 {

				reg = <0>;

				qcom,mempool-page-size = <4096>;

			};

			/* 64K Page Pool configuration */

			qcom,gpu-mempool@1 {

				reg = <1>;

				qcom,mempool-page-size = <65536>;

			};

		};



		/* Power levels */

		qcom,gpu-pwrlevels {

			#address-cells = <1>;

arch/arm/boot/dts/qcom/msm8952-gpu.dtsi

+20 −0
Original line number Diff line number Diff line
@@ -113,6 +113,26 @@ 
		qcom,pm-qos-active-latency = <601>;

		qcom,pm-qos-wakeup-latency = <401>;



		/* GPU Mempools */

		qcom,gpu-mempools {

			#address-cells= <1>;

			#size-cells = <0>;

			compatible = "qcom,gpu-mempools";



			qcom,mempool-max-pages = <32768>;



			/* 4K Page Pool configuration */

			qcom,gpu-mempool@0 {

				reg = <0>;

				qcom,mempool-page-size = <4096>;

			};

			/* 64K Page Pool configuration */

			qcom,gpu-mempool@1 {

				reg = <1>;

				qcom,mempool-page-size  = <65536>;

			};

		};



		/* Power levels */

		qcom,gpu-pwrlevels {

			#address-cells = <1>;