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Commit f37c8c2d authored by Hareesh Gundu's avatar Hareesh Gundu
Browse files

ARM: dts: msm: Add GPU mempools properties for all msm 



Add initial set of configuration for GPU mempools
to reserve page pools at init time of kgsl driver.

CRs-Fixed: 1064046
Change-Id: Ie6789e13be7316a0de43538b9e477920fa64c6bb
Signed-off-by: default avatarHareesh Gundu <hareeshg@codeaurora.org>
parent 78b64330

arch/arm/boot/dts/qcom/msm8909-gpu.dtsi

+20 −0
Original line number Diff line number Diff line
@@ -95,6 +95,26 @@ 
		qcom,pm-qos-active-latency = <701>;

		qcom,pm-qos-wakeup-latency = <701>;



		/* GPU Mempools */

		qcom,gpu-mempools {

			#address-cells= <1>;

			#size-cells = <0>;

			compatible = "qcom,gpu-mempools";



			qcom,mempool-max-pages = <32768>;



			/* 4K Page Pool configuration */

			qcom,gpu-mempool@0 {

				reg = <0>;

				qcom,mempool-page-size = <4096>;

			};

			/* 64K Page Pool configuration */

			qcom,gpu-mempool@1 {

				reg = <1>;

				qcom,mempool-page-size  = <65536>;

			};

		};



		/* Power levels */

		qcom,gpu-pwrlevels {

			#address-cells = <1>;

arch/arm/boot/dts/qcom/msm8917-gpu.dtsi

+20 −0
Original line number Diff line number Diff line
@@ -109,6 +109,26 @@ 
		coresight-child-list = <&funnel_mm>;

		coresight-child-ports = <6>;



		/* GPU Mempools */

		qcom,gpu-mempools {

			#address-cells= <1>;

			#size-cells = <0>;

			compatible = "qcom,gpu-mempools";



			qcom,mempool-max-pages = <32768>;



			/* 4K Page Pool configuration */

			qcom,gpu-mempool@0 {

				reg = <0>;

				qcom,mempool-page-size = <4096>;

			};

			/* 64K Page Pool configuration */

			qcom,gpu-mempool@1 {

				reg = <1>;

				qcom,mempool-page-size  = <65536>;

			};

		};



		/* Power levels */

		qcom,gpu-pwrlevels {

			#address-cells = <1>;

arch/arm/boot/dts/qcom/msm8937-gpu.dtsi

+20 −0
Original line number Diff line number Diff line
@@ -124,6 +124,26 @@ 
		/* Context aware jump target power level */

		qcom,ca-target-pwrlevel = <1>;



		/* GPU Mempools */

		qcom,gpu-mempools {

			#address-cells= <1>;

			#size-cells = <0>;

			compatible = "qcom,gpu-mempools";



			qcom,mempool-max-pages = <32768>;



			/* 4K Page Pool configuration */

			qcom,gpu-mempool@0 {

				reg = <0>;

				qcom,mempool-page-size = <4096>;

			};

			/* 64K Page Pool configuration */

			qcom,gpu-mempool@1 {

				reg = <1>;

				qcom,mempool-page-size = <65536>;

			};

		};



		/* Power levels */

		qcom,gpu-pwrlevels {

			#address-cells = <1>;

arch/arm/boot/dts/qcom/msm8952-gpu.dtsi

+20 −0
Original line number Diff line number Diff line
@@ -113,6 +113,26 @@ 
		qcom,pm-qos-active-latency = <601>;

		qcom,pm-qos-wakeup-latency = <401>;



		/* GPU Mempools */

		qcom,gpu-mempools {

			#address-cells= <1>;

			#size-cells = <0>;

			compatible = "qcom,gpu-mempools";



			qcom,mempool-max-pages = <32768>;



			/* 4K Page Pool configuration */

			qcom,gpu-mempool@0 {

				reg = <0>;

				qcom,mempool-page-size = <4096>;

			};

			/* 64K Page Pool configuration */

			qcom,gpu-mempool@1 {

				reg = <1>;

				qcom,mempool-page-size  = <65536>;

			};

		};



		/* Power levels */

		qcom,gpu-pwrlevels {

			#address-cells = <1>;

arch/arm/boot/dts/qcom/msm8953-gpu.dtsi

+20 −0
Original line number Diff line number Diff line
@@ -139,6 +139,26 @@ 
		/* Context aware jump target power level */

		qcom,ca-target-pwrlevel = <3>;



		/* GPU Mempools */

		qcom,gpu-mempools {

			#address-cells= <1>;

			#size-cells = <0>;

			compatible = "qcom,gpu-mempools";



			qcom,mempool-max-pages = <32768>;



			/* 4K Page Pool configuration */

			qcom,gpu-mempool@0 {

				reg = <0>;

				qcom,mempool-page-size = <4096>;

			};

			/* 64K Page Pool configuration */

			qcom,gpu-mempool@1 {

				reg = <1>;

				qcom,mempool-page-size  = <65536>;

			};

		};



		/* Power levels */

		qcom,gpu-pwrlevels {

			#address-cells = <1>;