Merge "power: qpnp-fg: fix error in configuring interrupt source for IMA" (0eb29b8b) · Commits · e / devices / android_kernel_xiaomi_markw

drivers/power/qpnp-fg.c

+6 −6

Original line number	Diff line number	Diff line
		/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
		/* Copyright (c) 2014-2016, The Linux Foundation. All rights reserved.
		*
		* This program is free software; you can redistribute it and/or modify
		* it under the terms of the GNU General Public License version 2 and
		@@ -1141,7 +1141,7 @@ static int fg_check_iacs_ready(struct fg_chip *chip)
		return 0;
		}

		#define IACL_SCLT BIT(5)
		#define IACS_SLCT BIT(5)
		static int __fg_interleaved_mem_write(struct fg_chip chip, u8 val,
		u16 address, int offset, int len)
		{
		@@ -1271,7 +1271,7 @@ static int __fg_interleaved_mem_read(struct fg_chip chip, u8 val, u16 address,
		return rc;
		}

		#define IMA_REQ_ACCESS (IACL_SCLT \| RIF_MEM_ACCESS_REQ)
		#define IMA_REQ_ACCESS (IACS_SLCT \| RIF_MEM_ACCESS_REQ)
		static int fg_interleaved_mem_config(struct fg_chip chip, u8 val,
		u16 address, int len, int offset, int op)
		{
		@@ -6155,12 +6155,12 @@ static int fg_setup_memif_offset(struct fg_chip *chip)
		if (chip->ima_supported) {
		/*
		* Change the FG_MEM_INT interrupt to track IACS_READY
		* condition instead of end-of-transation. This makes sure
		* condition instead of end-of-transaction. This makes sure
		* that the next transaction starts only after the hw is ready.
		*/
		rc = fg_masked_write(chip,
		chip->mem_base + chip->offset[MEM_INTF_CFG],
		IACS_INTR_SRC_SLCT, IACS_INTR_SRC_SLCT, 1);
		chip->mem_base + MEM_INTF_IMA_CFG, IACS_INTR_SRC_SLCT,
		IACS_INTR_SRC_SLCT, 1);
		if (rc) {
		pr_err("failed to configure interrupt source %d\n", rc);
		return rc;