drivers: GICv3: Add mb() after the read of the IAR1_EL1 and other registers

As per the GICv3 architecture spec section "Observability
of GIC Register Accsses", architecture execution of the "DSB"
gurantees that last interrupt identifier read from ICC_IAR{0,1}_EL1
is observable by the top-level Distributor and by accesses from
any processor to the top-level Distributor.

Same comment goes for the ICC_PMR_EL1 and ICC_SGI1R_EL1 too.

CRs-Fixed: 960754
Change-Id: I9c7bcdee51f71d369e2a6f04faf7a22c3c1381bc
Signed-off-by: Trilok Soni <tsoni@codeaurora.org>