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Commit 0dce4fbb authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: Use "qcom,thorium-arm-cortex-acc" enable-method"

parents 961ee161 896332fa

Documentation/devicetree/bindings/arm/cpus.txt

+1 −0
Original line number Diff line number Diff line
@@ -186,6 +186,7 @@ nodes to be present and contain the properties described below. 
			     "psci"

			     "spin-table"

			     "qcom,titanium-arm-cortex-acc"

			     "qcom,thorium-arm-cortex-acc"



			# On ARM 32-bit systems this property is optional and

			  can be one of:

Documentation/devicetree/bindings/arm/msm/l2ccc.txt

+1 −0
Original line number Diff line number Diff line
@@ -8,6 +8,7 @@ Required properties: 
- compatible:	Can be one of:

		"qcom,8916-l2ccc"

		"qcom,titanium-l2ccc"

		"qcom,thorium-l2ccc"

- reg:		This specifies the base address and size of

		the register region.

arch/arm/boot/dts/qcom/msmthorium-cpu.dtsi

+46 −54
Original line number Diff line number Diff line
@@ -18,135 +18,127 @@ 
		cpu-map {

			cluster0 {

				core0 {

					cpu = <&CPU0>;

					cpu = <&CPU4>;

				};

				core1 {

					cpu = <&CPU1>;

					cpu = <&CPU5>;

				};

				core2 {

					cpu = <&CPU2>;

					cpu = <&CPU6>;

				};

				core3 {

					cpu = <&CPU3>;

					cpu = <&CPU7>;

				};

			};



			cluster1 {

				core0 {

					cpu = <&CPU4>;

					cpu = <&CPU0>;

				};

				core1 {

					cpu = <&CPU5>;

					cpu = <&CPU1>;

				};

				core2 {

					cpu = <&CPU6>;

					cpu = <&CPU2>;

				};

				core3 {

					cpu = <&CPU7>;

					cpu = <&CPU3>;

				};

			};

		};



		CPU0: cpu@0 {

		CPU0: cpu@100 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x0>;

			enable-method = "spin-table";

			cpu-release-addr = <0x0 0x90000000>;

			reg = <0x100>;

			enable-method = "qcom,thorium-arm-cortex-acc";

			qcom,acc = <&acc0>;

			next-level-cache = <&L2_0>;

			L2_0: l2-cache {

			next-level-cache = <&L2_1>;

			L2_1: l2-cache {

			      compatible = "arm,arch-cache";

			      cache-level = <2>;

			      power-domain = <&l2ccc_0>;

			      power-domain = <&l2ccc_1>;

			};

		};



		CPU1: cpu@1 {

		CPU1: cpu@101 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x1>;

			enable-method = "spin-table";

			cpu-release-addr = <0x0 0x90000000>;

			reg = <0x101>;

			enable-method = "qcom,thorium-arm-cortex-acc";

			qcom,acc = <&acc1>;

			next-level-cache = <&L2_0>;

			next-level-cache = <&L2_1>;

		};



		CPU2: cpu@2 {

		CPU2: cpu@102 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x2>;

			enable-method = "spin-table";

			cpu-release-addr = <0x0 0x90000000>;

			reg = <0x102>;

			enable-method = "qcom,thorium-arm-cortex-acc";

			qcom,acc = <&acc2>;

			next-level-cache = <&L2_0>;

			next-level-cache = <&L2_1>;

		};



		CPU3: cpu@3 {

		CPU3: cpu@103 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x3>;

			enable-method = "spin-table";

			cpu-release-addr = <0x0 0x90000000>;

			reg = <0x103>;

			enable-method = "qcom,thorium-arm-cortex-acc";

			qcom,acc = <&acc3>;

			next-level-cache = <&L2_0>;

			next-level-cache = <&L2_1>;

		};



		CPU4: cpu@100 {

		CPU4: cpu@0 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x100>;

			enable-method = "spin-table";

			cpu-release-addr = <0x0 0x90000000>;

			reg = <0x0>;

			enable-method = "qcom,thorium-arm-cortex-acc";

			qcom,acc = <&acc4>;

			next-level-cache = <&L2_1>;

			L2_1: l2-cache {

			next-level-cache = <&L2_0>;

			L2_0: l2-cache {

			      compatible = "arm,arch-cache";

			      cache-level = <2>;

			      power-domain = <&l2ccc_1>;

			      power-domain = <&l2ccc_0>;

			};

		};



		CPU5: cpu@101 {

		CPU5: cpu@1 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x101>;

			enable-method = "spin-table";

			cpu-release-addr = <0x0 0x90000000>;

			reg = <0x1>;

			enable-method = "qcom,thorium-arm-cortex-acc";

			qcom,acc = <&acc5>;

			next-level-cache = <&L2_1>;

			next-level-cache = <&L2_0>;

		};



		CPU6: cpu@102 {

		CPU6: cpu@2 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x102>;

			enable-method = "spin-table";

			cpu-release-addr = <0x0 0x90000000>;

			reg = <0x2>;

			enable-method = "qcom,thorium-arm-cortex-acc";

			qcom,acc = <&acc6>;

			next-level-cache = <&L2_1>;

			next-level-cache = <&L2_0>;

		};



		CPU7: cpu@103 {

		CPU7: cpu@3 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x103>;

			enable-method = "spin-table";

			cpu-release-addr = <0x0 0x90000000>;

			reg = <0x3>;

			enable-method = "qcom,thorium-arm-cortex-acc";

			qcom,acc = <&acc7>;

			next-level-cache = <&L2_1>;

			next-level-cache = <&L2_0>;

		};

	};

};



&soc {

	l2ccc_0: clock-controller@b111000 {

		compatible = "qcom,8916-l2ccc";

		compatible = "qcom,thorium-l2ccc";

		reg = <0x0b111000 0x1000>;

	};



	l2ccc_1: clock-controller@b011000 {

		compatible = "qcom,8916-l2ccc";

		compatible = "qcom,thorium-l2ccc";

		reg = <0x0b011000 0x1000>;

	};

arch/arm/boot/dts/qcom/msmthorium-rumi.dts

+0 −2
Original line number Diff line number Diff line
@@ -13,8 +13,6 @@ 


/dts-v1/;



/memreserve/ 0x90000000 0x00000200;



#include "msmthorium.dtsi"



/ {

arch/arm/boot/dts/qcom/msmtitanium-cpu.dtsi

+26 −34
Original line number Diff line number Diff line
@@ -51,8 +51,7 @@ 
			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x0>;

			enable-method = "spin-table";

			cpu-release-addr = <0x0 0x90000000>;

			enable-method = "qcom,titanium-arm-cortex-acc";

			qcom,acc = <&acc0>;

			next-level-cache = <&L2_0>;

			L2_0: l2-cache {
@@ -65,9 +64,8 @@ 
		CPU1: cpu@1 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			enable-method = "qcom,titanium-arm-cortex-acc";

			reg = <0x1>;

			enable-method = "spin-table";

			cpu-release-addr = <0x0 0x90000000>;

			qcom,acc = <&acc1>;

			next-level-cache = <&L2_0>;

		};
@@ -75,9 +73,8 @@ 
		CPU2: cpu@2 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			enable-method = "qcom,titanium-arm-cortex-acc";

			reg = <0x2>;

			enable-method = "spin-table";

			cpu-release-addr = <0x0 0x90000000>;

			qcom,acc = <&acc2>;

			next-level-cache = <&L2_0>;

		};
@@ -85,9 +82,8 @@ 
		CPU3: cpu@3 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			enable-method = "qcom,titanium-arm-cortex-acc";

			reg = <0x3>;

			enable-method = "spin-table";

			cpu-release-addr = <0x0 0x90000000>;

			qcom,acc = <&acc3>;

			next-level-cache = <&L2_0>;

		};
@@ -95,9 +91,8 @@ 
		CPU4: cpu@100 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			enable-method = "qcom,titanium-arm-cortex-acc";

			reg = <0x100>;

			enable-method = "spin-table";

			cpu-release-addr = <0x0 0x90000000>;

			qcom,acc = <&acc4>;

			next-level-cache = <&L2_1>;

			L2_1: l2-cache {
@@ -110,9 +105,8 @@ 
		CPU5: cpu@101 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			enable-method = "qcom,titanium-arm-cortex-acc";

			reg = <0x101>;

			enable-method = "spin-table";

			cpu-release-addr = <0x0 0x90000000>;

			qcom,acc = <&acc5>;

			next-level-cache = <&L2_1>;

		};
@@ -120,9 +114,8 @@ 
		CPU6: cpu@102 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			enable-method = "qcom,titanium-arm-cortex-acc";

			reg = <0x102>;

			enable-method = "spin-table";

			cpu-release-addr = <0x0 0x90000000>;

			qcom,acc = <&acc6>;

			next-level-cache = <&L2_1>;

		};
@@ -130,9 +123,8 @@ 
		CPU7: cpu@103 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			enable-method = "qcom,titanium-arm-cortex-acc";

			reg = <0x103>;

			enable-method = "spin-table";

			cpu-release-addr = <0x0 0x90000000>;

			qcom,acc = <&acc7>;

			next-level-cache = <&L2_1>;

		};
@@ -141,52 +133,52 @@ 


&soc {

	l2ccc_0: clock-controller@b111000 {

		compatible = "qcom,8916-l2ccc";

		compatible = "qcom,titanium-l2ccc";

		reg = <0x0b111000 0x1000>;

	};



	l2ccc_1: clock-controller@b011000 {

		compatible = "qcom,8916-l2ccc";

		compatible = "qcom,titanium-l2ccc";

		reg = <0x0b011000 0x1000>;

	};



	acc0:clock-controller@b088000 {

	acc0:clock-controller@b188000 {

		compatible = "qcom,arm-cortex-acc";

		reg = <0x0b088000 0x1000>;

		reg = <0x0b188000 0x1000>;

	};



	acc1:clock-controller@b098000 {

	acc1:clock-controller@b198000 {

		compatible = "qcom,arm-cortex-acc";

		reg = <0x0b098000 0x1000>;

		reg = <0x0b198000 0x1000>;

	};



	acc2:clock-controller@b0a8000 {

	acc2:clock-controller@b1a8000 {

		compatible = "qcom,arm-cortex-acc";

		reg = <0x0b0a8000 0x1000>;

		reg = <0x0b1a8000 0x1000>;

	};



	acc3:clock-controller@b0b8000 {

	acc3:clock-controller@b1b8000 {

		compatible = "qcom,arm-cortex-acc";

		reg = <0x0b0b8000 0x1000>;

		reg = <0x0b1b8000 0x1000>;

	};



	acc4:clock-controller@b188000 {

	acc4:clock-controller@b088000 {

		compatible = "qcom,arm-cortex-acc";

		reg = <0x0b188000 0x1000>;

		reg = <0x0b088000 0x1000>;

	};



	acc5:clock-controller@b198000 {

	acc5:clock-controller@b098000 {

		compatible = "qcom,arm-cortex-acc";

		reg = <0x0b198000 0x1000>;

		reg = <0x0b098000 0x1000>;

	};



	acc6:clock-controller@b1a8000 {

	acc6:clock-controller@b0a8000 {

		compatible = "qcom,arm-cortex-acc";

		reg = <0x0b1a8000 0x1000>;

		reg = <0x0b0a8000 0x1000>;

	};



	acc7:clock-controller@b1b8000 {

	acc7:clock-controller@b0b8000 {

		compatible = "qcom,arm-cortex-acc";

		reg = <0x0b1b8000 0x1000>;

		reg = <0x0b0b8000 0x1000>;

	};

};