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Commit 896332fa authored by Prasad Sodagudi's avatar Prasad Sodagudi
Browse files

ARM: dts: msm: Use "qcom,thorium-arm-cortex-acc" enable-method 



Currently spin-table method is in use for msmthorium, so move
to "qcom,thorium-arm-cortex-acc" enable-method for msmthorium.

Change-Id: I3ebf28c22604c95e1574a413f574b61781006c70
Signed-off-by: default avatarPrasad Sodagudi <psodagud@codeaurora.org>
parent 653509ad

arch/arm/boot/dts/qcom/msmthorium-cpu.dtsi

+46 −54
Original line number Diff line number Diff line
@@ -18,135 +18,127 @@ 
		cpu-map {

			cluster0 {

				core0 {

					cpu = <&CPU0>;

					cpu = <&CPU4>;

				};

				core1 {

					cpu = <&CPU1>;

					cpu = <&CPU5>;

				};

				core2 {

					cpu = <&CPU2>;

					cpu = <&CPU6>;

				};

				core3 {

					cpu = <&CPU3>;

					cpu = <&CPU7>;

				};

			};



			cluster1 {

				core0 {

					cpu = <&CPU4>;

					cpu = <&CPU0>;

				};

				core1 {

					cpu = <&CPU5>;

					cpu = <&CPU1>;

				};

				core2 {

					cpu = <&CPU6>;

					cpu = <&CPU2>;

				};

				core3 {

					cpu = <&CPU7>;

					cpu = <&CPU3>;

				};

			};

		};



		CPU0: cpu@0 {

		CPU0: cpu@100 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x0>;

			enable-method = "spin-table";

			cpu-release-addr = <0x0 0x90000000>;

			reg = <0x100>;

			enable-method = "qcom,thorium-arm-cortex-acc";

			qcom,acc = <&acc0>;

			next-level-cache = <&L2_0>;

			L2_0: l2-cache {

			next-level-cache = <&L2_1>;

			L2_1: l2-cache {

			      compatible = "arm,arch-cache";

			      cache-level = <2>;

			      power-domain = <&l2ccc_0>;

			      power-domain = <&l2ccc_1>;

			};

		};



		CPU1: cpu@1 {

		CPU1: cpu@101 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x1>;

			enable-method = "spin-table";

			cpu-release-addr = <0x0 0x90000000>;

			reg = <0x101>;

			enable-method = "qcom,thorium-arm-cortex-acc";

			qcom,acc = <&acc1>;

			next-level-cache = <&L2_0>;

			next-level-cache = <&L2_1>;

		};



		CPU2: cpu@2 {

		CPU2: cpu@102 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x2>;

			enable-method = "spin-table";

			cpu-release-addr = <0x0 0x90000000>;

			reg = <0x102>;

			enable-method = "qcom,thorium-arm-cortex-acc";

			qcom,acc = <&acc2>;

			next-level-cache = <&L2_0>;

			next-level-cache = <&L2_1>;

		};



		CPU3: cpu@3 {

		CPU3: cpu@103 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x3>;

			enable-method = "spin-table";

			cpu-release-addr = <0x0 0x90000000>;

			reg = <0x103>;

			enable-method = "qcom,thorium-arm-cortex-acc";

			qcom,acc = <&acc3>;

			next-level-cache = <&L2_0>;

			next-level-cache = <&L2_1>;

		};



		CPU4: cpu@100 {

		CPU4: cpu@0 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x100>;

			enable-method = "spin-table";

			cpu-release-addr = <0x0 0x90000000>;

			reg = <0x0>;

			enable-method = "qcom,thorium-arm-cortex-acc";

			qcom,acc = <&acc4>;

			next-level-cache = <&L2_1>;

			L2_1: l2-cache {

			next-level-cache = <&L2_0>;

			L2_0: l2-cache {

			      compatible = "arm,arch-cache";

			      cache-level = <2>;

			      power-domain = <&l2ccc_1>;

			      power-domain = <&l2ccc_0>;

			};

		};



		CPU5: cpu@101 {

		CPU5: cpu@1 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x101>;

			enable-method = "spin-table";

			cpu-release-addr = <0x0 0x90000000>;

			reg = <0x1>;

			enable-method = "qcom,thorium-arm-cortex-acc";

			qcom,acc = <&acc5>;

			next-level-cache = <&L2_1>;

			next-level-cache = <&L2_0>;

		};



		CPU6: cpu@102 {

		CPU6: cpu@2 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x102>;

			enable-method = "spin-table";

			cpu-release-addr = <0x0 0x90000000>;

			reg = <0x2>;

			enable-method = "qcom,thorium-arm-cortex-acc";

			qcom,acc = <&acc6>;

			next-level-cache = <&L2_1>;

			next-level-cache = <&L2_0>;

		};



		CPU7: cpu@103 {

		CPU7: cpu@3 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x103>;

			enable-method = "spin-table";

			cpu-release-addr = <0x0 0x90000000>;

			reg = <0x3>;

			enable-method = "qcom,thorium-arm-cortex-acc";

			qcom,acc = <&acc7>;

			next-level-cache = <&L2_1>;

			next-level-cache = <&L2_0>;

		};

	};

};



&soc {

	l2ccc_0: clock-controller@b111000 {

		compatible = "qcom,8916-l2ccc";

		compatible = "qcom,thorium-l2ccc";

		reg = <0x0b111000 0x1000>;

	};



	l2ccc_1: clock-controller@b011000 {

		compatible = "qcom,8916-l2ccc";

		compatible = "qcom,thorium-l2ccc";

		reg = <0x0b011000 0x1000>;

	};

arch/arm/boot/dts/qcom/msmthorium-rumi.dts

+0 −2
Original line number Diff line number Diff line
@@ -13,8 +13,6 @@ 


/dts-v1/;



/memreserve/ 0x90000000 0x00000200;



#include "msmthorium.dtsi"



/ {