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Commit 0b9b80a6 authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "clk: msm: clock: Allow voting for gfx_mx rail via a new gpu dummy clock"

parents 5b5632a5 b40db36f

Documentation/devicetree/bindings/arm/msm/clock-controller.txt

+6 −5
Original line number Diff line number Diff line
@@ -62,15 +62,16 @@ Optional properties: 
- <pll>_analog-supply:	Some PLLs might have separate analog supply on some

			targets. These properties will be provided on those

			targets for specific PLLs.

- vdd_gpu_mx-supply:	MX rail supply for the GPU core.

- #clock_cells:		If this device will also be providing controllable

			clocks, the clock_cells property needs to be specified.

			This will allow the common clock device tree framework

			to recognize _this_ device node as a clock provider.

- qcom,dev-opp-list:	List of device nodes for which the drivers would need

			the Operating Performance Points(OPP). OPPs are the

			frequency/voltage pairs that the device can operate at.

			drivers can use the OPP library API to operate on the

			list of OPPs registered.

- qcom,<clk>-corner-<vers>: List of frequency voltage pairs that the clock can

			    operate at. Drivers can use the OPP library API to

			    operate on the list of OPPs registered using these

			    values.





Example:

	clock_rpm: qcom,rpmcc@fc4000000 {

arch/arm/boot/dts/qcom/msm8996-v2.dtsi

+7 −0
Original line number Diff line number Diff line
@@ -46,6 +46,13 @@ 
		<  300000000  3  4 >,

		<  500000000  4  5 >,

		<  604800000  5  7 >;

	qcom,gpufreq-mx-corner-v2=

		<	   0  0 >,

		<  125000000  4 >,

		<  214000000  4 >,

		<  315000000  4 >,

		<  500000000  5 >,

		<  604800000  7 >;

};



&gdsc_gpu_gx {

arch/arm/boot/dts/qcom/msm8996.dtsi

+9 −0
Original line number Diff line number Diff line
@@ -835,6 +835,7 @@ 
		vdd_gfx-supply = <&gfx_vreg>;

		gpu_handle = <&msm_gpu>;

		vdd_mx-supply = <&pm8994_s2_corner>;

		vdd_gpu_mx-supply = <&pm8994_s2_corner>;

		qcom,gfxfreq-corner-v0 =

			<	   0  0  0 >,

			<   19200000  2  4 >,
@@ -843,6 +844,14 @@ 
			<  205000000  3  4 >,

			<  360000000  4  5 >,

			<  480000000  5  7 >;

		qcom,gpufreq-mx-corner-v0 =

			<	   0  0 >,

			<   19200000  4 >,

			<   60000000  4 >,

			<  120000000  4 >,

			<  205000000  4 >,

			<  360000000  5 >,

			<  480000000  7 >;

		#clock-cells = <1>;

	};

drivers/clk/msm/clock-mmss-8996.c

+47 −10
Original line number Diff line number Diff line
@@ -76,6 +76,7 @@ static int vdd_mmpll4_levels[] = { 
static DEFINE_VDD_REGULATORS(vdd_mmpll4, VDD_DIG_NUM, 2, vdd_mmpll4_levels,

									NULL);

DEFINE_VDD_REGS_INIT(vdd_gfx, 2);

DEFINE_VDD_REGS_INIT(vdd_gpu_mx, 1);



static struct alpha_pll_masks pll_masks_p = {

	.lock_mask = BIT(31),
@@ -2316,6 +2317,15 @@ static struct branch_clk gpu_gx_gfx3d_clk = { 
	},

};



static struct fixed_clk gpu_mx_clk = {

	.c = {

		.dbg_name = "gpu_mx_clk",

		.vdd_class = &vdd_gpu_mx,

		.ops = &clk_ops_dummy,

		CLK_INIT(gpu_mx_clk.c),

	},

};



static struct branch_clk gpu_gx_rbbmtimer_clk = {

	.cbcr_reg = MMSS_GPU_GX_RBBMTIMER_CBCR,

	.has_sibling = 0,
@@ -3362,8 +3372,9 @@ static int of_get_fmax_vdd_class(struct platform_device *pdev, struct clk *c, 
								char *prop_name)

{

	struct device_node *of = pdev->dev.of_node;

	int prop_len, i;

	int prop_len, i, j;

	struct clk_vdd_class *vdd = c->vdd_class;

	int num = vdd->num_regulators + 1;

	u32 *array;



	if (!of_find_property(of, prop_name, &prop_len)) {
@@ -3372,19 +3383,19 @@ static int of_get_fmax_vdd_class(struct platform_device *pdev, struct clk *c, 
	}



	prop_len /= sizeof(u32);

	if (prop_len % 3) {

	if (prop_len % num) {

		dev_err(&pdev->dev, "bad length %d\n", prop_len);

		return -EINVAL;

	}



	prop_len /= 3;

	prop_len /= num;

	vdd->level_votes = devm_kzalloc(&pdev->dev, prop_len * sizeof(int),

					GFP_KERNEL);

	if (!vdd->level_votes)

		return -ENOMEM;



	vdd->vdd_uv = devm_kzalloc(&pdev->dev, prop_len * sizeof(int) * 2,

					GFP_KERNEL);

	vdd->vdd_uv = devm_kzalloc(&pdev->dev,

			prop_len * sizeof(int) * (num - 1), GFP_KERNEL);

	if (!vdd->vdd_uv)

		return -ENOMEM;
@@ -3394,15 +3405,17 @@ static int of_get_fmax_vdd_class(struct platform_device *pdev, struct clk *c, 
		return -ENOMEM;



	array = devm_kzalloc(&pdev->dev,

			prop_len * sizeof(u32) * 3, GFP_KERNEL);

			prop_len * sizeof(u32) * num, GFP_KERNEL);

	if (!array)

		return -ENOMEM;



	of_property_read_u32_array(of, prop_name, array, prop_len * 3);

	of_property_read_u32_array(of, prop_name, array, prop_len * num);

	for (i = 0; i < prop_len; i++) {

		c->fmax[i] = array[3 * i];

		vdd->vdd_uv[2 * i] = array[3 * i + 1];

		vdd->vdd_uv[2 * i + 1] = array[3 * i + 2];

		c->fmax[i] = array[num * i];

		for (j = 1; j < num; j++) {

			vdd->vdd_uv[(num - 1) * i + (j - 1)] =

						array[num * i + j];

		}

	}



	devm_kfree(&pdev->dev, array);
@@ -3652,6 +3665,7 @@ static struct clk_lookup msm_clocks_gpu_8996[] = { 
	CLK_LIST(gpu_ahb_clk),

	CLK_LIST(gpu_aon_isense_clk),

	CLK_LIST(gpu_gx_gfx3d_clk),

	CLK_LIST(gpu_mx_clk),

	CLK_LIST(gpu_gx_rbbmtimer_clk),

	CLK_LIST(gpu_gcc_dbg_clk),

};
@@ -3662,6 +3676,7 @@ static struct clk_lookup msm_clocks_gpu_8996_v2[] = { 
	CLK_LIST(gpu_ahb_clk),

	CLK_LIST(gpu_aon_isense_clk),

	CLK_LIST(gpu_gx_gfx3d_clk),

	CLK_LIST(gpu_mx_clk),

	CLK_LIST(gpu_gx_rbbmtimer_clk),

	CLK_LIST(gpu_gcc_dbg_clk),

};
@@ -3704,6 +3719,14 @@ int msm_gpucc_8996_probe(struct platform_device *pdev) 
		return PTR_ERR(reg);

	}



	reg = vdd_gpu_mx.regulator[0] = devm_regulator_get(&pdev->dev,

								"vdd_gpu_mx");

	if (IS_ERR(reg)) {

		if (PTR_ERR(reg) != -EPROBE_DEFER)

			dev_err(&pdev->dev, "Unable to get vdd_gpu_mx regulator!");

		return PTR_ERR(reg);

	}



	is_v2_gpu = of_device_is_compatible(pdev->dev.of_node,

						"qcom,gpucc-8996-v2");

	if (!is_v2_gpu) {
@@ -3714,6 +3737,13 @@ int msm_gpucc_8996_probe(struct platform_device *pdev) 
			return rc;

		}



		rc = of_get_fmax_vdd_class(pdev, &gpu_mx_clk.c,

					"qcom,gpufreq-mx-corner-v0");

		if (rc) {

			dev_err(&pdev->dev, "Unable to get gpu mx freq-corner mapping info\n");

			return rc;

		}



		rc = of_msm_clock_register(pdev->dev.of_node,

					msm_clocks_gpu_8996,

					ARRAY_SIZE(msm_clocks_gpu_8996));
@@ -3728,6 +3758,13 @@ int msm_gpucc_8996_probe(struct platform_device *pdev) 
			return rc;

		}



		rc = of_get_fmax_vdd_class(pdev, &gpu_mx_clk.c,

					"qcom,gpufreq-mx-corner-v2");

		if (rc) {

			dev_err(&pdev->dev, "Unable to get gpu mx freq-corner mapping info\n");

			return rc;

		}



		rc = of_msm_clock_register(pdev->dev.of_node,

					msm_clocks_gpu_8996_v2,

					ARRAY_SIZE(msm_clocks_gpu_8996_v2));

include/dt-bindings/clock/msm-clocks-8996.h

+1 −0
Original line number Diff line number Diff line
@@ -409,6 +409,7 @@ 
#define clk_gpu_ahb_clk			0xf97f1d43

#define clk_gpu_aon_isense_clk		0xa9e9b297

#define clk_gpu_gx_gfx3d_clk		0xb7ece823

#define clk_gpu_mx_clk			0xb80ccedf

#define clk_gpu_gx_rbbmtimer_clk	0xdeba634e

#define clk_mdss_ahb_clk		0x684ccb41

#define clk_mdss_axi_clk		0xcc07d687