Loading drivers/gpu/msm/kgsl_iommu.c +7 −5 Original line number Diff line number Diff line Loading @@ -1178,7 +1178,7 @@ kgsl_iommu_unmap(struct kgsl_pagetable *pt, return 0; if (kgsl_memdesc_has_guard_page(memdesc)) range += kgsl_memdesc_guard_page_size(memdesc); range += kgsl_memdesc_guard_page_size(pt->mmu, memdesc); if (kgsl_memdesc_is_secured(memdesc)) { Loading Loading @@ -1245,8 +1245,9 @@ int _iommu_add_guard_page(struct kgsl_pagetable *pt, * mapped to save 1MB of memory if CPZ is not used. */ if (kgsl_memdesc_is_secured(memdesc)) { struct scatterlist *sg; unsigned int sgp_size = pt->mmu->secure_align_mask + 1; if (!kgsl_secure_guard_page_memdesc.physaddr) { if (!kgsl_secure_guard_page_memdesc.sgt) { if (kgsl_allocate_user(pt->mmu->device, &kgsl_secure_guard_page_memdesc, pt, sgp_size, sgp_size, Loading @@ -1257,12 +1258,13 @@ int _iommu_add_guard_page(struct kgsl_pagetable *pt, } } physaddr = kgsl_secure_guard_page_memdesc.physaddr; sg = kgsl_secure_guard_page_memdesc.sgt->sgl; physaddr = page_to_phys(sg_page(sg)); } _iommu_sync_mmu_pc(pt->mmu->device, true); ret = iommu_map(iommu_pt->domain, gpuaddr, physaddr, kgsl_memdesc_guard_page_size(memdesc), kgsl_memdesc_guard_page_size(pt->mmu, memdesc), protflags & ~IOMMU_WRITE); _iommu_sync_mmu_pc(pt->mmu->device, false); if (ret) { Loading Loading @@ -1897,7 +1899,7 @@ static int kgsl_iommu_get_gpuaddr(struct kgsl_pagetable *pagetable, return -EINVAL; if (kgsl_memdesc_has_guard_page(memdesc)) size += kgsl_memdesc_guard_page_size(memdesc); size += kgsl_memdesc_guard_page_size(pagetable->mmu, memdesc); align = 1 << kgsl_memdesc_get_align(memdesc); Loading drivers/gpu/msm/kgsl_mmu.c +2 −2 Original line number Diff line number Diff line Loading @@ -764,7 +764,7 @@ kgsl_mmu_map(struct kgsl_pagetable *pagetable, /* Add space for the guard page when allocating the mmu VA. */ size = memdesc->size; if (kgsl_memdesc_has_guard_page(memdesc)) size += kgsl_memdesc_guard_page_size(memdesc); size += kgsl_memdesc_guard_page_size(pagetable->mmu, memdesc); ret = pagetable->pt_ops->mmu_map(pagetable, memdesc); Loading Loading @@ -837,7 +837,7 @@ kgsl_mmu_unmap(struct kgsl_pagetable *pagetable, /* Add space for the guard page when freeing the mmu VA. */ size = memdesc->size; if (kgsl_memdesc_has_guard_page(memdesc)) size += kgsl_memdesc_guard_page_size(memdesc); size += kgsl_memdesc_guard_page_size(pagetable->mmu, memdesc); start_addr = memdesc->gpuaddr; end_addr = (memdesc->gpuaddr + size); Loading drivers/gpu/msm/kgsl_sharedmem.c +1 −1 Original line number Diff line number Diff line Loading @@ -420,7 +420,7 @@ static void kgsl_page_alloc_free(struct kgsl_memdesc *memdesc) /* Secure buffers need to be unlocked before being freed */ if (memdesc->priv & KGSL_MEMDESC_TZ_LOCKED) { int ret; int dest_perms = PERM_READ | PERM_WRITE; int dest_perms = PERM_READ | PERM_WRITE | PERM_EXEC; int source_vm = VMID_CP_PIXEL; int dest_vm = VMID_HLOS; Loading drivers/gpu/msm/kgsl_sharedmem.h +4 −2 Original line number Diff line number Diff line Loading @@ -221,9 +221,11 @@ kgsl_memdesc_has_guard_page(const struct kgsl_memdesc *memdesc) * Returns guard page size */ static inline int kgsl_memdesc_guard_page_size(const struct kgsl_memdesc *memdesc) kgsl_memdesc_guard_page_size(const struct kgsl_mmu *mmu, const struct kgsl_memdesc *memdesc) { return kgsl_memdesc_is_secured(memdesc) ? SZ_1M : PAGE_SIZE; return kgsl_memdesc_is_secured(memdesc) ? mmu->secure_align_mask + 1 : PAGE_SIZE; } /* Loading include/soc/qcom/secure_buffer.h +1 −0 Original line number Diff line number Diff line Loading @@ -29,6 +29,7 @@ #define PERM_READ 0x4 #define PERM_WRITE 0x2 #define PERM_EXEC 0x1 #ifdef CONFIG_MSM_SECURE_BUFFER int msm_secure_table(struct sg_table *table); Loading Loading
drivers/gpu/msm/kgsl_iommu.c +7 −5 Original line number Diff line number Diff line Loading @@ -1178,7 +1178,7 @@ kgsl_iommu_unmap(struct kgsl_pagetable *pt, return 0; if (kgsl_memdesc_has_guard_page(memdesc)) range += kgsl_memdesc_guard_page_size(memdesc); range += kgsl_memdesc_guard_page_size(pt->mmu, memdesc); if (kgsl_memdesc_is_secured(memdesc)) { Loading Loading @@ -1245,8 +1245,9 @@ int _iommu_add_guard_page(struct kgsl_pagetable *pt, * mapped to save 1MB of memory if CPZ is not used. */ if (kgsl_memdesc_is_secured(memdesc)) { struct scatterlist *sg; unsigned int sgp_size = pt->mmu->secure_align_mask + 1; if (!kgsl_secure_guard_page_memdesc.physaddr) { if (!kgsl_secure_guard_page_memdesc.sgt) { if (kgsl_allocate_user(pt->mmu->device, &kgsl_secure_guard_page_memdesc, pt, sgp_size, sgp_size, Loading @@ -1257,12 +1258,13 @@ int _iommu_add_guard_page(struct kgsl_pagetable *pt, } } physaddr = kgsl_secure_guard_page_memdesc.physaddr; sg = kgsl_secure_guard_page_memdesc.sgt->sgl; physaddr = page_to_phys(sg_page(sg)); } _iommu_sync_mmu_pc(pt->mmu->device, true); ret = iommu_map(iommu_pt->domain, gpuaddr, physaddr, kgsl_memdesc_guard_page_size(memdesc), kgsl_memdesc_guard_page_size(pt->mmu, memdesc), protflags & ~IOMMU_WRITE); _iommu_sync_mmu_pc(pt->mmu->device, false); if (ret) { Loading Loading @@ -1897,7 +1899,7 @@ static int kgsl_iommu_get_gpuaddr(struct kgsl_pagetable *pagetable, return -EINVAL; if (kgsl_memdesc_has_guard_page(memdesc)) size += kgsl_memdesc_guard_page_size(memdesc); size += kgsl_memdesc_guard_page_size(pagetable->mmu, memdesc); align = 1 << kgsl_memdesc_get_align(memdesc); Loading
drivers/gpu/msm/kgsl_mmu.c +2 −2 Original line number Diff line number Diff line Loading @@ -764,7 +764,7 @@ kgsl_mmu_map(struct kgsl_pagetable *pagetable, /* Add space for the guard page when allocating the mmu VA. */ size = memdesc->size; if (kgsl_memdesc_has_guard_page(memdesc)) size += kgsl_memdesc_guard_page_size(memdesc); size += kgsl_memdesc_guard_page_size(pagetable->mmu, memdesc); ret = pagetable->pt_ops->mmu_map(pagetable, memdesc); Loading Loading @@ -837,7 +837,7 @@ kgsl_mmu_unmap(struct kgsl_pagetable *pagetable, /* Add space for the guard page when freeing the mmu VA. */ size = memdesc->size; if (kgsl_memdesc_has_guard_page(memdesc)) size += kgsl_memdesc_guard_page_size(memdesc); size += kgsl_memdesc_guard_page_size(pagetable->mmu, memdesc); start_addr = memdesc->gpuaddr; end_addr = (memdesc->gpuaddr + size); Loading
drivers/gpu/msm/kgsl_sharedmem.c +1 −1 Original line number Diff line number Diff line Loading @@ -420,7 +420,7 @@ static void kgsl_page_alloc_free(struct kgsl_memdesc *memdesc) /* Secure buffers need to be unlocked before being freed */ if (memdesc->priv & KGSL_MEMDESC_TZ_LOCKED) { int ret; int dest_perms = PERM_READ | PERM_WRITE; int dest_perms = PERM_READ | PERM_WRITE | PERM_EXEC; int source_vm = VMID_CP_PIXEL; int dest_vm = VMID_HLOS; Loading
drivers/gpu/msm/kgsl_sharedmem.h +4 −2 Original line number Diff line number Diff line Loading @@ -221,9 +221,11 @@ kgsl_memdesc_has_guard_page(const struct kgsl_memdesc *memdesc) * Returns guard page size */ static inline int kgsl_memdesc_guard_page_size(const struct kgsl_memdesc *memdesc) kgsl_memdesc_guard_page_size(const struct kgsl_mmu *mmu, const struct kgsl_memdesc *memdesc) { return kgsl_memdesc_is_secured(memdesc) ? SZ_1M : PAGE_SIZE; return kgsl_memdesc_is_secured(memdesc) ? mmu->secure_align_mask + 1 : PAGE_SIZE; } /* Loading
include/soc/qcom/secure_buffer.h +1 −0 Original line number Diff line number Diff line Loading @@ -29,6 +29,7 @@ #define PERM_READ 0x4 #define PERM_WRITE 0x2 #define PERM_EXEC 0x1 #ifdef CONFIG_MSM_SECURE_BUFFER int msm_secure_table(struct sg_table *table); Loading