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Commit 0b7cd862 authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: update cpu mapping for etm and jtag on msm8937"

parents cf3d6f99 085c634e

arch/arm/boot/dts/qcom/msm8937-coresight.dtsi

+16 −16
Original line number Diff line number Diff line
@@ -237,7 +237,7 @@ 
		coresight-outports = <0>;

		coresight-child-list = <&funnel_apss>;

		coresight-child-ports = <4>;

		coresight-etm-cpu = <&CPU4>;

		coresight-etm-cpu = <&CPU0>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;
@@ -255,7 +255,7 @@ 
		coresight-outports = <0>;

		coresight-child-list = <&funnel_apss>;

		coresight-child-ports = <5>;

		coresight-etm-cpu = <&CPU5>;

		coresight-etm-cpu = <&CPU1>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;
@@ -273,7 +273,7 @@ 
		coresight-outports = <0>;

		coresight-child-list = <&funnel_apss>;

		coresight-child-ports = <6>;

		coresight-etm-cpu = <&CPU6>;

		coresight-etm-cpu = <&CPU2>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;
@@ -291,7 +291,7 @@ 
		coresight-outports = <0>;

		coresight-child-list = <&funnel_apss>;

		coresight-child-ports = <7>;

		coresight-etm-cpu = <&CPU7>;

		coresight-etm-cpu = <&CPU3>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;
@@ -309,7 +309,7 @@ 
		coresight-outports = <0>;

		coresight-child-list = <&funnel_apss>;

		coresight-child-ports = <0>;

		coresight-etm-cpu = <&CPU0>;

		coresight-etm-cpu = <&CPU4>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;
@@ -327,7 +327,7 @@ 
		coresight-outports = <0>;

		coresight-child-list = <&funnel_apss>;

		coresight-child-ports = <1>;

		coresight-etm-cpu = <&CPU1>;

		coresight-etm-cpu = <&CPU5>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;
@@ -345,7 +345,7 @@ 
		coresight-outports = <0>;

		coresight-child-list = <&funnel_apss>;

		coresight-child-ports = <2>;

		coresight-etm-cpu = <&CPU2>;

		coresight-etm-cpu = <&CPU6>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;
@@ -363,7 +363,7 @@ 
		coresight-outports = <0>;

		coresight-child-list = <&funnel_apss>;

		coresight-child-ports = <3>;

		coresight-etm-cpu = <&CPU3>;

		coresight-etm-cpu = <&CPU7>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;
@@ -620,7 +620,7 @@ 
		coresight-id = <35>;

		coresight-name = "coresight-cti-cpu0";

		coresight-nr-inports = <0>;

		coresight-cti-cpu = <&CPU4>;

		coresight-cti-cpu = <&CPU0>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;
@@ -635,7 +635,7 @@ 
		coresight-id = <36>;

		coresight-name = "coresight-cti-cpu1";

		coresight-nr-inports = <0>;

		coresight-cti-cpu = <&CPU5>;

		coresight-cti-cpu = <&CPU1>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;
@@ -650,7 +650,7 @@ 
		coresight-id = <37>;

		coresight-name = "coresight-cti-cpu2";

		coresight-nr-inports = <0>;

		coresight-cti-cpu = <&CPU6>;

		coresight-cti-cpu = <&CPU2>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;
@@ -665,7 +665,7 @@ 
		coresight-id = <38>;

		coresight-name = "coresight-cti-cpu3";

		coresight-nr-inports = <0>;

		coresight-cti-cpu = <&CPU7>;

		coresight-cti-cpu = <&CPU3>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;
@@ -680,7 +680,7 @@ 
		coresight-id = <39>;

		coresight-name = "coresight-cti-cpu4";

		coresight-nr-inports = <0>;

		coresight-cti-cpu = <&CPU0>;

		coresight-cti-cpu = <&CPU4>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;
@@ -695,7 +695,7 @@ 
		coresight-id = <40>;

		coresight-name = "coresight-cti-cpu5";

		coresight-nr-inports = <0>;

		coresight-cti-cpu = <&CPU1>;

		coresight-cti-cpu = <&CPU5>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;
@@ -710,7 +710,7 @@ 
		coresight-id = <41>;

		coresight-name = "coresight-cti-cpu6";

		coresight-nr-inports = <0>;

		coresight-cti-cpu = <&CPU2>;

		coresight-cti-cpu = <&CPU6>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;
@@ -725,7 +725,7 @@ 
		coresight-id = <42>;

		coresight-name = "coresight-cti-cpu7";

		coresight-nr-inports = <0>;

		coresight-cti-cpu = <&CPU3>;

		coresight-cti-cpu = <&CPU7>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

arch/arm/boot/dts/qcom/msm8937.dtsi

+8 −8
Original line number Diff line number Diff line
@@ -1070,7 +1070,7 @@ 
		      <0x61b0000 0x1000>;

		reg-names = "etm-base", "debug-base";



		qcom,coresight-jtagmm-cpu = <&CPU4>;

		qcom,coresight-jtagmm-cpu = <&CPU0>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;
@@ -1083,7 +1083,7 @@ 
		      <0x61b2000 0x1000>;

		reg-names = "etm-base", "debug-base";



		qcom,coresight-jtagmm-cpu = <&CPU5>;

		qcom,coresight-jtagmm-cpu = <&CPU1>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;
@@ -1096,7 +1096,7 @@ 
		      <0x61b4000 0x1000>;

		reg-names = "etm-base", "debug-base";



		qcom,coresight-jtagmm-cpu = <&CPU6>;

		qcom,coresight-jtagmm-cpu = <&CPU2>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;
@@ -1109,7 +1109,7 @@ 
		      <0x61b6000 0x1000>;

		reg-names = "etm-base", "debug-base";



		qcom,coresight-jtagmm-cpu = <&CPU7>;

		qcom,coresight-jtagmm-cpu = <&CPU3>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;
@@ -1122,7 +1122,7 @@ 
		      <0x6190000 0x1000>;

		reg-names = "etm-base", "debug-base";



		qcom,coresight-jtagmm-cpu = <&CPU0>;

		qcom,coresight-jtagmm-cpu = <&CPU4>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;
@@ -1135,7 +1135,7 @@ 
		      <0x6192000 0x1000>;

		reg-names = "etm-base", "debug-base";



		qcom,coresight-jtagmm-cpu = <&CPU1>;

		qcom,coresight-jtagmm-cpu = <&CPU5>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;
@@ -1148,7 +1148,7 @@ 
		      <0x6194000 0x1000>;

		reg-names = "etm-base", "debug-base";



		qcom,coresight-jtagmm-cpu = <&CPU2>;

		qcom,coresight-jtagmm-cpu = <&CPU6>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;
@@ -1161,7 +1161,7 @@ 
		      <0x6196000 0x1000>;

		reg-names = "etm-base", "debug-base";



		qcom,coresight-jtagmm-cpu = <&CPU3>;

		qcom,coresight-jtagmm-cpu = <&CPU7>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;