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Commit 085c634e authored by Xiaogang Cui's avatar Xiaogang Cui
Browse files

ARM: dts: msm: update cpu mapping for etm and jtag on msm8937 



The cpu mapping for power and performance cluster. Need to update
the etm/cpu mapping for CoreSight as well for MSM8937.

Change-Id: I7c4e4e441a47be5a6378cc7c17597cc066f5f52a
Signed-off-by: default avatarXiaogang Cui <xiaogang@codeaurora.org>
parent 718b9859

arch/arm/boot/dts/qcom/msm8937-coresight.dtsi

+16 −16
Original line number Diff line number Diff line
@@ -182,7 +182,7 @@ 
		coresight-outports = <0>;

		coresight-child-list = <&funnel_apss>;

		coresight-child-ports = <4>;

		coresight-etm-cpu = <&CPU4>;

		coresight-etm-cpu = <&CPU0>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;
@@ -200,7 +200,7 @@ 
		coresight-outports = <0>;

		coresight-child-list = <&funnel_apss>;

		coresight-child-ports = <5>;

		coresight-etm-cpu = <&CPU5>;

		coresight-etm-cpu = <&CPU1>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;
@@ -218,7 +218,7 @@ 
		coresight-outports = <0>;

		coresight-child-list = <&funnel_apss>;

		coresight-child-ports = <6>;

		coresight-etm-cpu = <&CPU6>;

		coresight-etm-cpu = <&CPU2>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;
@@ -236,7 +236,7 @@ 
		coresight-outports = <0>;

		coresight-child-list = <&funnel_apss>;

		coresight-child-ports = <7>;

		coresight-etm-cpu = <&CPU7>;

		coresight-etm-cpu = <&CPU3>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;
@@ -254,7 +254,7 @@ 
		coresight-outports = <0>;

		coresight-child-list = <&funnel_apss>;

		coresight-child-ports = <0>;

		coresight-etm-cpu = <&CPU0>;

		coresight-etm-cpu = <&CPU4>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;
@@ -272,7 +272,7 @@ 
		coresight-outports = <0>;

		coresight-child-list = <&funnel_apss>;

		coresight-child-ports = <1>;

		coresight-etm-cpu = <&CPU1>;

		coresight-etm-cpu = <&CPU5>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;
@@ -290,7 +290,7 @@ 
		coresight-outports = <0>;

		coresight-child-list = <&funnel_apss>;

		coresight-child-ports = <2>;

		coresight-etm-cpu = <&CPU2>;

		coresight-etm-cpu = <&CPU6>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;
@@ -308,7 +308,7 @@ 
		coresight-outports = <0>;

		coresight-child-list = <&funnel_apss>;

		coresight-child-ports = <3>;

		coresight-etm-cpu = <&CPU3>;

		coresight-etm-cpu = <&CPU7>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;
@@ -565,7 +565,7 @@ 
		coresight-id = <34>;

		coresight-name = "coresight-cti-cpu0";

		coresight-nr-inports = <0>;

		coresight-cti-cpu = <&CPU4>;

		coresight-cti-cpu = <&CPU0>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;
@@ -580,7 +580,7 @@ 
		coresight-id = <35>;

		coresight-name = "coresight-cti-cpu1";

		coresight-nr-inports = <0>;

		coresight-cti-cpu = <&CPU5>;

		coresight-cti-cpu = <&CPU1>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;
@@ -595,7 +595,7 @@ 
		coresight-id = <36>;

		coresight-name = "coresight-cti-cpu2";

		coresight-nr-inports = <0>;

		coresight-cti-cpu = <&CPU6>;

		coresight-cti-cpu = <&CPU2>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;
@@ -610,7 +610,7 @@ 
		coresight-id = <37>;

		coresight-name = "coresight-cti-cpu3";

		coresight-nr-inports = <0>;

		coresight-cti-cpu = <&CPU7>;

		coresight-cti-cpu = <&CPU3>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;
@@ -625,7 +625,7 @@ 
		coresight-id = <38>;

		coresight-name = "coresight-cti-cpu4";

		coresight-nr-inports = <0>;

		coresight-cti-cpu = <&CPU0>;

		coresight-cti-cpu = <&CPU4>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;
@@ -640,7 +640,7 @@ 
		coresight-id = <39>;

		coresight-name = "coresight-cti-cpu5";

		coresight-nr-inports = <0>;

		coresight-cti-cpu = <&CPU1>;

		coresight-cti-cpu = <&CPU5>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;
@@ -655,7 +655,7 @@ 
		coresight-id = <40>;

		coresight-name = "coresight-cti-cpu6";

		coresight-nr-inports = <0>;

		coresight-cti-cpu = <&CPU2>;

		coresight-cti-cpu = <&CPU6>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;
@@ -670,7 +670,7 @@ 
		coresight-id = <41>;

		coresight-name = "coresight-cti-cpu7";

		coresight-nr-inports = <0>;

		coresight-cti-cpu = <&CPU3>;

		coresight-cti-cpu = <&CPU7>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

arch/arm/boot/dts/qcom/msm8937.dtsi

+8 −8
Original line number Diff line number Diff line
@@ -1058,7 +1058,7 @@ 
		      <0x61b0000 0x1000>;

		reg-names = "etm-base", "debug-base";



		qcom,coresight-jtagmm-cpu = <&CPU4>;

		qcom,coresight-jtagmm-cpu = <&CPU0>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;
@@ -1071,7 +1071,7 @@ 
		      <0x61b2000 0x1000>;

		reg-names = "etm-base", "debug-base";



		qcom,coresight-jtagmm-cpu = <&CPU5>;

		qcom,coresight-jtagmm-cpu = <&CPU1>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;
@@ -1084,7 +1084,7 @@ 
		      <0x61b4000 0x1000>;

		reg-names = "etm-base", "debug-base";



		qcom,coresight-jtagmm-cpu = <&CPU6>;

		qcom,coresight-jtagmm-cpu = <&CPU2>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;
@@ -1097,7 +1097,7 @@ 
		      <0x61b6000 0x1000>;

		reg-names = "etm-base", "debug-base";



		qcom,coresight-jtagmm-cpu = <&CPU7>;

		qcom,coresight-jtagmm-cpu = <&CPU3>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;
@@ -1110,7 +1110,7 @@ 
		      <0x6190000 0x1000>;

		reg-names = "etm-base", "debug-base";



		qcom,coresight-jtagmm-cpu = <&CPU0>;

		qcom,coresight-jtagmm-cpu = <&CPU4>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;
@@ -1123,7 +1123,7 @@ 
		      <0x6192000 0x1000>;

		reg-names = "etm-base", "debug-base";



		qcom,coresight-jtagmm-cpu = <&CPU1>;

		qcom,coresight-jtagmm-cpu = <&CPU5>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;
@@ -1136,7 +1136,7 @@ 
		      <0x6194000 0x1000>;

		reg-names = "etm-base", "debug-base";



		qcom,coresight-jtagmm-cpu = <&CPU2>;

		qcom,coresight-jtagmm-cpu = <&CPU6>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;
@@ -1149,7 +1149,7 @@ 
		      <0x6196000 0x1000>;

		reg-names = "etm-base", "debug-base";



		qcom,coresight-jtagmm-cpu = <&CPU3>;

		qcom,coresight-jtagmm-cpu = <&CPU7>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;