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Commit 718b9859 authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "clk: msm: 8937: Fixes for GCC clocks for msm8937"

parents 609720f6 35f51b8f

arch/arm/boot/dts/qcom/msm8937.dtsi

+2 −3
Original line number Diff line number Diff line
@@ -1753,9 +1753,8 @@ 
};



&gdsc_oxili_gx {

	clock-names = "core_root_clk", "gmem_clk";

	clocks =<&clock_gcc clk_gfx3d_clk_src>,

		<&clock_gcc clk_gcc_oxili_gmem_clk>;

	clock-names = "core_root_clk";

	clocks =<&clock_gcc clk_gfx3d_clk_src>;

	qcom,enable-root-clk;

	qcom,clk-dis-wait-val = <0x5>;

	status = "okay";

drivers/clk/msm/clock-gcc-8952.c

+6 −2
Original line number Diff line number Diff line
@@ -1338,7 +1338,7 @@ static struct rcg_clk byte0_clk_src = { 
	.base = &virt_bases[GCC_BASE],

	.c = {

		.dbg_name = "byte0_clk_src",

		.ops = &clk_ops_pixel_multiparent,

		.ops = &clk_ops_byte_multiparent,

		.flags = CLKFLAG_NO_RATE_CACHE,

		VDD_DIG_FMAX_MAP2(LOWER, 120000000, NOMINAL, 187500000),

		CLK_INIT(byte0_clk_src.c),
@@ -1375,7 +1375,7 @@ static struct rcg_clk byte1_clk_src = { 
		.base = &virt_bases[GCC_BASE],

		.c = {

			.dbg_name = "byte1_clk_src",

			.ops = &clk_ops_pixel_multiparent,

			.ops = &clk_ops_byte_multiparent,

			.flags = CLKFLAG_NO_RATE_CACHE,

			VDD_DIG_FMAX_MAP2(LOWER, 125000000, NOMINAL, 187500000),

			CLK_INIT(byte1_clk_src.c),
@@ -4019,6 +4019,10 @@ static int msm_gcc_probe(struct platform_device *pdev) 
	if (compat_bin) {

		gpll0_clk_src.c.parent = &gpll0_clk_src_8937.c;

		gpll0_ao_clk_src.c.parent = &gpll0_ao_clk_src_8937.c;

		/* Oxili Ocmem in GX rail: OXILI_GMEM_CLAMP_IO */

		regval = readl_relaxed(GCC_REG_BASE(GX_DOMAIN_MISC));

		regval &= ~BIT(0);

		writel_relaxed(regval, GCC_REG_BASE(GX_DOMAIN_MISC));

		override_for_8937();

	} else {

		gpll0_clk_src.c.parent = &gpll0_clk_src_8952.c;

include/dt-bindings/clock/msm-clocks-hwio-8952.h

+1 −0
Original line number Diff line number Diff line
@@ -19,6 +19,7 @@ 
#define GPLL3_MODE			0x22000

#define GPLL4_MODE			0x24000

#define GPLL4_STATUS			0x24024

#define GX_DOMAIN_MISC			0x5B00C

#define SYS_MM_NOC_AXI_CBCR		0x3D008

#define BIMC_GFX_CBCR			0x59034

#define MSS_CFG_AHB_CBCR		0x49000