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Commit 0b52b756 authored by Prasad Sodagudi's avatar Prasad Sodagudi
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ARM: dts: msm: Enable L1/L2 cache dump for couple of SoCs 



Enable L1/L2 cache dumps feature for msm8937, msm8917 and
msm8953 targets.

Change-Id: I14a7596e343aeb6b8df8ee1a4f3c2d729c299e18
Signed-off-by: default avatarPrasad Sodagudi <psodagud@codeaurora.org>
parent 626b2bb0
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