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Commit 090f4b6a authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/radeon: enable mgcg on SI 



Now that the CP is no longer reset and cg is properly
disabled in when appropriate in the dpm code we can
now enable mgcg (medium grained clockgating).

Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 4cb0add2

drivers/gpu/drm/radeon/radeon_asic.c

+5 −5
Original line number Diff line number Diff line
@@ -2338,7 +2338,7 @@ int radeon_asic_init(struct radeon_device *rdev) 
		switch (rdev->family) {

		case CHIP_TAHITI:

			rdev->cg_flags =

				/*RADEON_CG_SUPPORT_GFX_MGCG |*/

				RADEON_CG_SUPPORT_GFX_MGCG |

				RADEON_CG_SUPPORT_GFX_MGLS |

				/*RADEON_CG_SUPPORT_GFX_CGCG |*/

				RADEON_CG_SUPPORT_GFX_CGLS |
@@ -2355,7 +2355,7 @@ int radeon_asic_init(struct radeon_device *rdev) 
			break;

		case CHIP_PITCAIRN:

			rdev->cg_flags =

				/*RADEON_CG_SUPPORT_GFX_MGCG |*/

				RADEON_CG_SUPPORT_GFX_MGCG |

				RADEON_CG_SUPPORT_GFX_MGLS |

				/*RADEON_CG_SUPPORT_GFX_CGCG |*/

				RADEON_CG_SUPPORT_GFX_CGLS |
@@ -2374,7 +2374,7 @@ int radeon_asic_init(struct radeon_device *rdev) 
			break;

		case CHIP_VERDE:

			rdev->cg_flags =

				/*RADEON_CG_SUPPORT_GFX_MGCG |*/

				RADEON_CG_SUPPORT_GFX_MGCG |

				RADEON_CG_SUPPORT_GFX_MGLS |

				/*RADEON_CG_SUPPORT_GFX_CGCG |*/

				RADEON_CG_SUPPORT_GFX_CGLS |
@@ -2395,7 +2395,7 @@ int radeon_asic_init(struct radeon_device *rdev) 
			break;

		case CHIP_OLAND:

			rdev->cg_flags =

				/*RADEON_CG_SUPPORT_GFX_MGCG |*/

				RADEON_CG_SUPPORT_GFX_MGCG |

				RADEON_CG_SUPPORT_GFX_MGLS |

				/*RADEON_CG_SUPPORT_GFX_CGCG |*/

				RADEON_CG_SUPPORT_GFX_CGLS |
@@ -2413,7 +2413,7 @@ int radeon_asic_init(struct radeon_device *rdev) 
			break;

		case CHIP_HAINAN:

			rdev->cg_flags =

				/*RADEON_CG_SUPPORT_GFX_MGCG |*/

				RADEON_CG_SUPPORT_GFX_MGCG |

				RADEON_CG_SUPPORT_GFX_MGLS |

				/*RADEON_CG_SUPPORT_GFX_CGCG |*/

				RADEON_CG_SUPPORT_GFX_CGLS |