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Commit 4cb0add2 authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/radeon: handle cg in SI dpm code 



Clockgating needs to be disabled around certain parts
of dpm setup otherwise the smc gets into a bad state
and dpm doesn't work properly.

Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 5594a558

drivers/gpu/drm/radeon/si_dpm.c

+38 −0
Original line number Diff line number Diff line
@@ -1753,6 +1753,9 @@ static int si_calculate_sclk_params(struct radeon_device *rdev, 
				    u32 engine_clock,

				    SISLANDS_SMC_SCLK_VALUE *sclk);



extern void si_update_cg(struct radeon_device *rdev,

			 u32 block, bool enable);



static struct si_power_info *si_get_pi(struct radeon_device *rdev)

{

        struct si_power_info *pi = rdev->pm.dpm.priv;
@@ -5759,6 +5762,13 @@ int si_dpm_enable(struct radeon_device *rdev) 
	struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;

	int ret;



	si_update_cg(rdev, (RADEON_CG_BLOCK_GFX |

			    RADEON_CG_BLOCK_MC |

			    RADEON_CG_BLOCK_SDMA |

			    RADEON_CG_BLOCK_BIF |

			    RADEON_CG_BLOCK_UVD |

			    RADEON_CG_BLOCK_HDP), false);



	if (si_is_smc_running(rdev))

		return -EINVAL;

	if (pi->voltage_control)
@@ -5878,6 +5888,13 @@ int si_dpm_enable(struct radeon_device *rdev) 


	si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true);



	si_update_cg(rdev, (RADEON_CG_BLOCK_GFX |

			    RADEON_CG_BLOCK_MC |

			    RADEON_CG_BLOCK_SDMA |

			    RADEON_CG_BLOCK_BIF |

			    RADEON_CG_BLOCK_UVD |

			    RADEON_CG_BLOCK_HDP), true);



	ni_update_current_ps(rdev, boot_ps);



	return 0;
@@ -5888,6 +5905,13 @@ void si_dpm_disable(struct radeon_device *rdev) 
	struct rv7xx_power_info *pi = rv770_get_pi(rdev);

	struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;



	si_update_cg(rdev, (RADEON_CG_BLOCK_GFX |

			    RADEON_CG_BLOCK_MC |

			    RADEON_CG_BLOCK_SDMA |

			    RADEON_CG_BLOCK_BIF |

			    RADEON_CG_BLOCK_UVD |

			    RADEON_CG_BLOCK_HDP), false);



	if (!si_is_smc_running(rdev))

		return;

	si_disable_ulv(rdev);
@@ -5952,6 +5976,13 @@ int si_dpm_set_power_state(struct radeon_device *rdev) 
	struct radeon_ps *old_ps = &eg_pi->current_rps;

	int ret;



	si_update_cg(rdev, (RADEON_CG_BLOCK_GFX |

			    RADEON_CG_BLOCK_MC |

			    RADEON_CG_BLOCK_SDMA |

			    RADEON_CG_BLOCK_BIF |

			    RADEON_CG_BLOCK_UVD |

			    RADEON_CG_BLOCK_HDP), false);



	ret = si_disable_ulv(rdev);

	if (ret) {

		DRM_ERROR("si_disable_ulv failed\n");
@@ -6050,6 +6081,13 @@ int si_dpm_set_power_state(struct radeon_device *rdev) 
		return ret;

	}



	si_update_cg(rdev, (RADEON_CG_BLOCK_GFX |

			    RADEON_CG_BLOCK_MC |

			    RADEON_CG_BLOCK_SDMA |

			    RADEON_CG_BLOCK_BIF |

			    RADEON_CG_BLOCK_UVD |

			    RADEON_CG_BLOCK_HDP), true);



	return 0;

}