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Commit 05352690 authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "clk: msm: clock-gcc: Fix the divider values for blsp uart clock"

parents 5bb78670 cebb6e1f

drivers/clk/msm/clock-alpha-pll.c

+7 −2
Original line number Diff line number Diff line
@@ -526,8 +526,13 @@ static int __calibrate_alpha_pll(struct alpha_pll_clk *pll) 
		pr_err("alpha pll: not in a valid vco range\n");

		return -EINVAL;

	}

	calibration_freq = (vco_tbl[vco_val].min_freq +

			    vco_tbl[vco_val].max_freq)/2;

	/*

	 * As during slewing plls vco_sel won't be allowed to change, vco table

	 * should have only one entry table, i.e. index = 0, find the

	 * calibration frequency.

	 */

	calibration_freq = (vco_tbl[0].min_freq +

					vco_tbl[0].max_freq)/2;



	freq_hz = round_rate_up(pll, calibration_freq, &l_val, &a_val);

	if (freq_hz != calibration_freq) {

drivers/clk/msm/clock-gcc-8952.c

+1 −1
Original line number Diff line number Diff line
@@ -917,7 +917,7 @@ static struct clk_freq_tbl ftbl_gcc_blsp1_2_uart1_2_apps_clk[] = { 
	F( 56000000,	gpll0,	1,	7,	100),

	F( 58982400,	gpll0,	1,	1152,	15625),

	F( 60000000,	gpll0,	1,	3,	40),

	F( 64000000,	gpll0, 12,	1,	 2),

	F( 64000000,	gpll0,  1,	2,	25),

	F_END

};