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Commit 027f27c4 authored by John David Anglin's avatar John David Anglin Committed by Helge Deller
Browse files

parisc: disable preemption while flushing D- or I-caches through TMPALIAS region 



It is necessary to disable preemption during cache flushes done through the
TMPALIAS region to ensure that the TLB setup is not clobbered by another flush.

Signed-off-by: default avatarJohn David Anglin <dave.anglin@bell.net>
Signed-off-by: default avatarHelge Deller <deller@gmx.de>
parent b54cb233

arch/parisc/include/asm/cacheflush.h

+2 −0
Original line number Diff line number Diff line
@@ -115,7 +115,9 @@ flush_anon_page(struct vm_area_struct *vma, struct page *page, unsigned long vma 
{

	if (PageAnon(page)) {

		flush_tlb_page(vma, vmaddr);

		preempt_disable();

		flush_dcache_page_asm(page_to_phys(page), vmaddr);

		preempt_enable();

	}

}

arch/parisc/kernel/cache.c

+2 −0
Original line number Diff line number Diff line
@@ -267,9 +267,11 @@ static inline void 
__flush_cache_page(struct vm_area_struct *vma, unsigned long vmaddr,

		   unsigned long physaddr)

{

	preempt_disable();

	flush_dcache_page_asm(physaddr, vmaddr);

	if (vma->vm_flags & VM_EXEC)

		flush_icache_page_asm(physaddr, vmaddr);

	preempt_enable();

}



void flush_dcache_page(struct page *page)