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Commit cf6ed9a6 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'ras-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull RAS updates from Ingo Molnar:
 "Main changes in this cycle were:

   - AMD MCE/RAS handling updates (Yazen Ghannam, Aravind
     Gopalakrishnan)

   - Cleanups (Borislav Petkov)

   - logging fix (Tony Luck)"

* 'ras-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  x86/RAS: Add SMCA support to AMD Error Injector
  EDAC, mce_amd: Detect SMCA using X86_FEATURE_SMCA
  x86/mce: Update AMD mcheck init to use cpu_has() facilities
  x86/cpu: Add detection of AMD RAS Capabilities
  x86/mce/AMD: Save an indentation level in prepare_threshold_block()
  x86/mce/AMD: Disable LogDeferredInMcaStat for SMCA systems
  x86/mce/AMD: Log Deferred Errors using SMCA MCA_DE{STAT,ADDR} registers
  x86/mce: Detect local MCEs properly
  x86/mce: Look in genpool instead of mcelog for pending error records
  x86/mce: Detect and use SMCA-specific msr_ops
  x86/mce: Define vendor-specific MSR accessors
  x86/mce: Carve out writes to MCx_STATUS and MCx_CTL
  x86/mce: Grade uncorrected errors for SMCA-enabled systems
  x86/mce: Log MCEs after a warm rest on AMD, Fam17h and later
  x86/mce: Remove explicit smp_rmb() when starting CPUs sync
  x86/RAS: Rename AMD MCE injector config item
parents 36db171c 754a9230

arch/x86/include/asm/cpufeature.h

+1 −0
Original line number Diff line number Diff line
@@ -27,6 +27,7 @@ enum cpuid_leafs 
	CPUID_6_EAX,

	CPUID_8000_000A_EDX,

	CPUID_7_ECX,

	CPUID_8000_0007_EBX,

};



#ifdef CONFIG_X86_FEATURE_NAMES

arch/x86/include/asm/cpufeatures.h

+6 −1
Original line number Diff line number Diff line
@@ -12,7 +12,7 @@ 
/*

 * Defines x86 CPU feature bits

 */

#define NCAPINTS	17	/* N 32-bit words worth of info */

#define NCAPINTS	18	/* N 32-bit words worth of info */

#define NBUGINTS	1	/* N 32-bit bug flags */



/*
@@ -282,6 +282,11 @@ 
#define X86_FEATURE_PKU		(16*32+ 3) /* Protection Keys for Userspace */

#define X86_FEATURE_OSPKE	(16*32+ 4) /* OS Protection Keys Enable */



/* AMD-defined CPU features, CPUID level 0x80000007 (ebx), word 17 */

#define X86_FEATURE_OVERFLOW_RECOV (17*32+0) /* MCA overflow recovery support */

#define X86_FEATURE_SUCCOR	(17*32+1) /* Uncorrectable error containment and recovery */

#define X86_FEATURE_SMCA	(17*32+3) /* Scalable MCA */



/*

 * BUG word(s)

 */

arch/x86/include/asm/mce.h

+19 −0
Original line number Diff line number Diff line
@@ -104,13 +104,23 @@ 
#define MCE_LOG_SIGNATURE	"MACHINECHECK"



/* AMD Scalable MCA */

#define MSR_AMD64_SMCA_MC0_CTL		0xc0002000

#define MSR_AMD64_SMCA_MC0_STATUS	0xc0002001

#define MSR_AMD64_SMCA_MC0_ADDR		0xc0002002

#define MSR_AMD64_SMCA_MC0_MISC0	0xc0002003

#define MSR_AMD64_SMCA_MC0_CONFIG	0xc0002004

#define MSR_AMD64_SMCA_MC0_IPID		0xc0002005

#define MSR_AMD64_SMCA_MC0_DESTAT	0xc0002008

#define MSR_AMD64_SMCA_MC0_DEADDR	0xc0002009

#define MSR_AMD64_SMCA_MC0_MISC1	0xc000200a

#define MSR_AMD64_SMCA_MCx_CTL(x)	(MSR_AMD64_SMCA_MC0_CTL + 0x10*(x))

#define MSR_AMD64_SMCA_MCx_STATUS(x)	(MSR_AMD64_SMCA_MC0_STATUS + 0x10*(x))

#define MSR_AMD64_SMCA_MCx_ADDR(x)	(MSR_AMD64_SMCA_MC0_ADDR + 0x10*(x))

#define MSR_AMD64_SMCA_MCx_MISC(x)	(MSR_AMD64_SMCA_MC0_MISC0 + 0x10*(x))

#define MSR_AMD64_SMCA_MCx_CONFIG(x)	(MSR_AMD64_SMCA_MC0_CONFIG + 0x10*(x))

#define MSR_AMD64_SMCA_MCx_IPID(x)	(MSR_AMD64_SMCA_MC0_IPID + 0x10*(x))

#define MSR_AMD64_SMCA_MCx_DESTAT(x)	(MSR_AMD64_SMCA_MC0_DESTAT + 0x10*(x))

#define MSR_AMD64_SMCA_MCx_DEADDR(x)	(MSR_AMD64_SMCA_MC0_DEADDR + 0x10*(x))

#define MSR_AMD64_SMCA_MCx_MISCy(x, y)	((MSR_AMD64_SMCA_MC0_MISC1 + y) + (0x10*(x)))



/*
@@ -168,9 +178,18 @@ struct mce_vendor_flags { 


	      __reserved_0	: 61;

};



struct mca_msr_regs {

	u32 (*ctl)	(int bank);

	u32 (*status)	(int bank);

	u32 (*addr)	(int bank);

	u32 (*misc)	(int bank);

};



extern struct mce_vendor_flags mce_flags;



extern struct mca_config mca_cfg;

extern struct mca_msr_regs msr_ops;

extern void mce_register_decode_chain(struct notifier_block *nb);

extern void mce_unregister_decode_chain(struct notifier_block *nb);

arch/x86/kernel/cpu/common.c

+7 −3
Original line number Diff line number Diff line
@@ -717,6 +717,13 @@ void get_cpu_cap(struct cpuinfo_x86 *c) 
		}

	}



	if (c->extended_cpuid_level >= 0x80000007) {

		cpuid(0x80000007, &eax, &ebx, &ecx, &edx);



		c->x86_capability[CPUID_8000_0007_EBX] = ebx;

		c->x86_power = edx;

	}



	if (c->extended_cpuid_level >= 0x80000008) {

		cpuid(0x80000008, &eax, &ebx, &ecx, &edx);
@@ -729,9 +736,6 @@ void get_cpu_cap(struct cpuinfo_x86 *c) 
		c->x86_phys_bits = 36;

#endif



	if (c->extended_cpuid_level >= 0x80000007)

		c->x86_power = cpuid_edx(0x80000007);



	if (c->extended_cpuid_level >= 0x8000000a)

		c->x86_capability[CPUID_8000_000A_EDX] = cpuid_edx(0x8000000a);

arch/x86/kernel/cpu/mcheck/mce-genpool.c

+46 −0
Original line number Diff line number Diff line
@@ -26,6 +26,52 @@ static struct gen_pool *mce_evt_pool; 
static LLIST_HEAD(mce_event_llist);

static char gen_pool_buf[MCE_POOLSZ];



/*

 * Compare the record "t" with each of the records on list "l" to see if

 * an equivalent one is present in the list.

 */

static bool is_duplicate_mce_record(struct mce_evt_llist *t, struct mce_evt_llist *l)

{

	struct mce_evt_llist *node;

	struct mce *m1, *m2;



	m1 = &t->mce;



	llist_for_each_entry(node, &l->llnode, llnode) {

		m2 = &node->mce;



		if (!mce_cmp(m1, m2))

			return true;

	}

	return false;

}



/*

 * The system has panicked - we'd like to peruse the list of MCE records

 * that have been queued, but not seen by anyone yet.  The list is in

 * reverse time order, so we need to reverse it. While doing that we can

 * also drop duplicate records (these were logged because some banks are

 * shared between cores or by all threads on a socket).

 */

struct llist_node *mce_gen_pool_prepare_records(void)

{

	struct llist_node *head;

	LLIST_HEAD(new_head);

	struct mce_evt_llist *node, *t;



	head = llist_del_all(&mce_event_llist);

	if (!head)

		return NULL;



	/* squeeze out duplicates while reversing order */

	llist_for_each_entry_safe(node, t, head, llnode) {

		if (!is_duplicate_mce_record(node, t))

			llist_add(&node->llnode, &new_head);

	}



	return new_head.first;

}



void mce_gen_pool_process(void)

{

	struct llist_node *head;