Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 754a9230 authored by Yazen Ghannam's avatar Yazen Ghannam Committed by Ingo Molnar
Browse files

x86/RAS: Add SMCA support to AMD Error Injector 



Use SMCA MSRs when writing to MCA_{STATUS,ADDR,MISC} and
MCA_DE{STAT,ADDR} when injecting Deferred Errors on SMCA platforms.

Signed-off-by: default avatarYazen Ghannam <Yazen.Ghannam@amd.com>
Signed-off-by: default avatarBorislav Petkov <bp@suse.de>
Cc: Andy Lutomirski <luto@amacapital.net>
Cc: Aravind Gopalakrishnan <aravindksg.lkml@gmail.com>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Brian Gerst <brgerst@gmail.com>
Cc: Denys Vlasenko <dvlasenk@redhat.com>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Tony Luck <tony.luck@intel.com>
Cc: linux-edac <linux-edac@vger.kernel.org>
Link: http://lkml.kernel.org/r/1462971509-3856-8-git-send-email-bp@alien8.de


Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
parent a348ed83

arch/x86/ras/mce_amd_inj.c

+25 −6
Original line number Original line Diff line number Diff line
@@ -290,6 +290,24 @@ static void do_inject(void) 
	wrmsr_on_cpu(cpu, MSR_IA32_MCG_STATUS,

	wrmsr_on_cpu(cpu, MSR_IA32_MCG_STATUS,

		     (u32)mcg_status, (u32)(mcg_status >> 32));

		     (u32)mcg_status, (u32)(mcg_status >> 32));





	if (boot_cpu_has(X86_FEATURE_SMCA)) {

		if (inj_type == DFR_INT_INJ) {

			wrmsr_on_cpu(cpu, MSR_AMD64_SMCA_MCx_DESTAT(b),

				     (u32)i_mce.status, (u32)(i_mce.status >> 32));



			wrmsr_on_cpu(cpu, MSR_AMD64_SMCA_MCx_DEADDR(b),

				     (u32)i_mce.addr, (u32)(i_mce.addr >> 32));

		} else {

			wrmsr_on_cpu(cpu, MSR_AMD64_SMCA_MCx_STATUS(b),

				     (u32)i_mce.status, (u32)(i_mce.status >> 32));



			wrmsr_on_cpu(cpu, MSR_AMD64_SMCA_MCx_ADDR(b),

				     (u32)i_mce.addr, (u32)(i_mce.addr >> 32));

		}



		wrmsr_on_cpu(cpu, MSR_AMD64_SMCA_MCx_MISC(b),

			     (u32)i_mce.misc, (u32)(i_mce.misc >> 32));

	} else {

		wrmsr_on_cpu(cpu, MSR_IA32_MCx_STATUS(b),

		wrmsr_on_cpu(cpu, MSR_IA32_MCx_STATUS(b),

			     (u32)i_mce.status, (u32)(i_mce.status >> 32));

			     (u32)i_mce.status, (u32)(i_mce.status >> 32));
@@ -298,6 +316,7 @@ static void do_inject(void) 




		wrmsr_on_cpu(cpu, MSR_IA32_MCx_MISC(b),

		wrmsr_on_cpu(cpu, MSR_IA32_MCx_MISC(b),

			     (u32)i_mce.misc, (u32)(i_mce.misc >> 32));

			     (u32)i_mce.misc, (u32)(i_mce.misc >> 32));

	}





	toggle_hw_mce_inject(cpu, false);

	toggle_hw_mce_inject(cpu, false);