Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit c5f2ac92 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'fixes-3.3-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc 

Arnd Bergmann says:
 "Another set of arm-soc bug fixes on top of v3.3-rc5.  The few larger
  bits are all for devices that still need to get set up in board code.

  Only three platforms are in this set of fixes: omap2+, pxa and lpc32xx."

* tag 'fixes-3.3-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (22 commits)
  ARM: LPC32xx: serial.c: Fixed loop limit
  ARM: LPC32xx: serial.c: HW bug workaround
  ARM: LPC32xx: irq.c: Clear latched event
  ARM: LPC32xx: Fix interrupt controller init
  ARM: LPC32xx: Fix irq on GPI_28
  ARM: OMAP2: fix mailbox init code
  ARM: OMAP2+: gpmc-smsc911x: add required smsc911x regulators
  ARM: OMAP1: Fix out-of-bounds array access for Innovator
  OMAP3 EVM: remove out-of-bounds array access of gpio_leds
  ARM: OMAP: Fix build error when mmc_omap is built as module
  ARM: OMAP: Fix kernel panic with HSMMC when twl4030_gpio is a module
  pxa/hx4700: add platform device and I2C info for AK4641 codec
  arch/arm/mach-pxa/: included linux/gpio.h twice
  arch/arm/mach-mmp/: some files include some headers twice
  ARM: pxa: fix error handling in pxa2xx_drv_pcmcia_probe
  ARM: pxa: fix including linux/gpio.h twice
  ARM: pxa: fix mixed declarations and code in sharpsl_pm
  ARM: pxa: fix wrong parsing gpio event on spitz
  ARM: OMAP2+: usb-host: fix compile warning
  ARM: OMAP4: Move the barrier memboclk_steal() as part of reserve callback
  ...
parents 88ebdda6 f2273ecd

arch/arm/mach-lpc32xx/include/mach/irqs.h

+1 −1
Original line number Original line Diff line number Diff line
@@ -61,7 +61,7 @@ 
 */

 */

#define IRQ_LPC32XX_JTAG_COMM_TX	LPC32XX_SIC1_IRQ(1)

#define IRQ_LPC32XX_JTAG_COMM_TX	LPC32XX_SIC1_IRQ(1)

#define IRQ_LPC32XX_JTAG_COMM_RX	LPC32XX_SIC1_IRQ(2)

#define IRQ_LPC32XX_JTAG_COMM_RX	LPC32XX_SIC1_IRQ(2)

#define IRQ_LPC32XX_GPI_11		LPC32XX_SIC1_IRQ(4)

#define IRQ_LPC32XX_GPI_28		LPC32XX_SIC1_IRQ(4)

#define IRQ_LPC32XX_TS_P		LPC32XX_SIC1_IRQ(6)

#define IRQ_LPC32XX_TS_P		LPC32XX_SIC1_IRQ(6)

#define IRQ_LPC32XX_TS_IRQ		LPC32XX_SIC1_IRQ(7)

#define IRQ_LPC32XX_TS_IRQ		LPC32XX_SIC1_IRQ(7)

#define IRQ_LPC32XX_TS_AUX		LPC32XX_SIC1_IRQ(8)

#define IRQ_LPC32XX_TS_AUX		LPC32XX_SIC1_IRQ(8)

arch/arm/mach-lpc32xx/irq.c

+20 −5
Original line number Original line Diff line number Diff line
@@ -118,6 +118,10 @@ static const struct lpc32xx_event_info lpc32xx_events[NR_IRQS] = { 
		.event_group = &lpc32xx_event_pin_regs,

		.event_group = &lpc32xx_event_pin_regs,

		.mask = LPC32XX_CLKPWR_EXTSRC_GPI_06_BIT,

		.mask = LPC32XX_CLKPWR_EXTSRC_GPI_06_BIT,

	},

	},

	[IRQ_LPC32XX_GPI_28] = {

		.event_group = &lpc32xx_event_pin_regs,

		.mask = LPC32XX_CLKPWR_EXTSRC_GPI_28_BIT,

	},

	[IRQ_LPC32XX_GPIO_00] = {

	[IRQ_LPC32XX_GPIO_00] = {

		.event_group = &lpc32xx_event_int_regs,

		.event_group = &lpc32xx_event_int_regs,

		.mask = LPC32XX_CLKPWR_INTSRC_GPIO_00_BIT,

		.mask = LPC32XX_CLKPWR_INTSRC_GPIO_00_BIT,
@@ -305,9 +309,18 @@ static int lpc32xx_irq_wake(struct irq_data *d, unsigned int state) 




		if (state)

		if (state)

			eventreg |= lpc32xx_events[d->irq].mask;

			eventreg |= lpc32xx_events[d->irq].mask;

		else

		else {

			eventreg &= ~lpc32xx_events[d->irq].mask;

			eventreg &= ~lpc32xx_events[d->irq].mask;





			/*

			 * When disabling the wakeup, clear the latched

			 * event

			 */

			__raw_writel(lpc32xx_events[d->irq].mask,

				lpc32xx_events[d->irq].

				event_group->rawstat_reg);

		}



		__raw_writel(eventreg,

		__raw_writel(eventreg,

			lpc32xx_events[d->irq].event_group->enab_reg);

			lpc32xx_events[d->irq].event_group->enab_reg);
@@ -380,13 +393,15 @@ void __init lpc32xx_init_irq(void) 




	/* Setup SIC1 */

	/* Setup SIC1 */

	__raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_SIC1_BASE));

	__raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_SIC1_BASE));

	__raw_writel(MIC_APR_DEFAULT, LPC32XX_INTC_POLAR(LPC32XX_SIC1_BASE));

	__raw_writel(SIC1_APR_DEFAULT, LPC32XX_INTC_POLAR(LPC32XX_SIC1_BASE));

	__raw_writel(MIC_ATR_DEFAULT, LPC32XX_INTC_ACT_TYPE(LPC32XX_SIC1_BASE));

	__raw_writel(SIC1_ATR_DEFAULT,

				LPC32XX_INTC_ACT_TYPE(LPC32XX_SIC1_BASE));





	/* Setup SIC2 */

	/* Setup SIC2 */

	__raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_SIC2_BASE));

	__raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_SIC2_BASE));

	__raw_writel(MIC_APR_DEFAULT, LPC32XX_INTC_POLAR(LPC32XX_SIC2_BASE));

	__raw_writel(SIC2_APR_DEFAULT, LPC32XX_INTC_POLAR(LPC32XX_SIC2_BASE));

	__raw_writel(MIC_ATR_DEFAULT, LPC32XX_INTC_ACT_TYPE(LPC32XX_SIC2_BASE));

	__raw_writel(SIC2_ATR_DEFAULT,

				LPC32XX_INTC_ACT_TYPE(LPC32XX_SIC2_BASE));





	/* Configure supported IRQ's */

	/* Configure supported IRQ's */

	for (i = 0; i < NR_IRQS; i++) {

	for (i = 0; i < NR_IRQS; i++) {

arch/arm/mach-lpc32xx/serial.c

+19 −1
Original line number Original line Diff line number Diff line
@@ -88,6 +88,7 @@ struct uartinit { 
	char *uart_ck_name;

	char *uart_ck_name;

	u32 ck_mode_mask;

	u32 ck_mode_mask;

	void __iomem *pdiv_clk_reg;

	void __iomem *pdiv_clk_reg;

	resource_size_t mapbase;

};

};





static struct uartinit uartinit_data[] __initdata = {

static struct uartinit uartinit_data[] __initdata = {
@@ -97,6 +98,7 @@ static struct uartinit uartinit_data[] __initdata = { 
		.ck_mode_mask =

		.ck_mode_mask =

			LPC32XX_UART_CLKMODE_LOAD(LPC32XX_UART_CLKMODE_ON, 5),

			LPC32XX_UART_CLKMODE_LOAD(LPC32XX_UART_CLKMODE_ON, 5),

		.pdiv_clk_reg = LPC32XX_CLKPWR_UART5_CLK_CTRL,

		.pdiv_clk_reg = LPC32XX_CLKPWR_UART5_CLK_CTRL,

		.mapbase = LPC32XX_UART5_BASE,

	},

	},

#endif

#endif

#ifdef CONFIG_ARCH_LPC32XX_UART3_SELECT

#ifdef CONFIG_ARCH_LPC32XX_UART3_SELECT
@@ -105,6 +107,7 @@ static struct uartinit uartinit_data[] __initdata = { 
		.ck_mode_mask =

		.ck_mode_mask =

			LPC32XX_UART_CLKMODE_LOAD(LPC32XX_UART_CLKMODE_ON, 3),

			LPC32XX_UART_CLKMODE_LOAD(LPC32XX_UART_CLKMODE_ON, 3),

		.pdiv_clk_reg = LPC32XX_CLKPWR_UART3_CLK_CTRL,

		.pdiv_clk_reg = LPC32XX_CLKPWR_UART3_CLK_CTRL,

		.mapbase = LPC32XX_UART3_BASE,

	},

	},

#endif

#endif

#ifdef CONFIG_ARCH_LPC32XX_UART4_SELECT

#ifdef CONFIG_ARCH_LPC32XX_UART4_SELECT
@@ -113,6 +116,7 @@ static struct uartinit uartinit_data[] __initdata = { 
		.ck_mode_mask =

		.ck_mode_mask =

			LPC32XX_UART_CLKMODE_LOAD(LPC32XX_UART_CLKMODE_ON, 4),

			LPC32XX_UART_CLKMODE_LOAD(LPC32XX_UART_CLKMODE_ON, 4),

		.pdiv_clk_reg = LPC32XX_CLKPWR_UART4_CLK_CTRL,

		.pdiv_clk_reg = LPC32XX_CLKPWR_UART4_CLK_CTRL,

		.mapbase = LPC32XX_UART4_BASE,

	},

	},

#endif

#endif

#ifdef CONFIG_ARCH_LPC32XX_UART6_SELECT

#ifdef CONFIG_ARCH_LPC32XX_UART6_SELECT
@@ -121,6 +125,7 @@ static struct uartinit uartinit_data[] __initdata = { 
		.ck_mode_mask =

		.ck_mode_mask =

			LPC32XX_UART_CLKMODE_LOAD(LPC32XX_UART_CLKMODE_ON, 6),

			LPC32XX_UART_CLKMODE_LOAD(LPC32XX_UART_CLKMODE_ON, 6),

		.pdiv_clk_reg = LPC32XX_CLKPWR_UART6_CLK_CTRL,

		.pdiv_clk_reg = LPC32XX_CLKPWR_UART6_CLK_CTRL,

		.mapbase = LPC32XX_UART6_BASE,

	},

	},

#endif

#endif

};

};
@@ -165,11 +170,24 @@ void __init lpc32xx_serial_init(void) 




		/* pre-UART clock divider set to 1 */

		/* pre-UART clock divider set to 1 */

		__raw_writel(0x0101, uartinit_data[i].pdiv_clk_reg);

		__raw_writel(0x0101, uartinit_data[i].pdiv_clk_reg);



		/*

		 * Force a flush of the RX FIFOs to work around a

		 * HW bug

		 */

		puart = uartinit_data[i].mapbase;

		__raw_writel(0xC1, LPC32XX_UART_IIR_FCR(puart));

		__raw_writel(0x00, LPC32XX_UART_DLL_FIFO(puart));

		j = LPC32XX_SUART_FIFO_SIZE;

		while (j--)

			tmp = __raw_readl(

				LPC32XX_UART_DLL_FIFO(puart));

		__raw_writel(0, LPC32XX_UART_IIR_FCR(puart));

	}

	}





	/* This needs to be done after all UART clocks are setup */

	/* This needs to be done after all UART clocks are setup */

	__raw_writel(clkmodes, LPC32XX_UARTCTL_CLKMODE);

	__raw_writel(clkmodes, LPC32XX_UARTCTL_CLKMODE);

	for (i = 0; i < ARRAY_SIZE(uartinit_data) - 1; i++) {

	for (i = 0; i < ARRAY_SIZE(uartinit_data); i++) {

		/* Force a flush of the RX FIFOs to work around a HW bug */

		/* Force a flush of the RX FIFOs to work around a HW bug */

		puart = serial_std_platform_data[i].mapbase;

		puart = serial_std_platform_data[i].mapbase;

		__raw_writel(0xC1, LPC32XX_UART_IIR_FCR(puart));

		__raw_writel(0xC1, LPC32XX_UART_IIR_FCR(puart));

arch/arm/mach-mmp/aspenite.c

+0 −1
Original line number Original line Diff line number Diff line
@@ -17,7 +17,6 @@ 
#include <linux/mtd/partitions.h>

#include <linux/mtd/partitions.h>

#include <linux/mtd/nand.h>

#include <linux/mtd/nand.h>

#include <linux/interrupt.h>

#include <linux/interrupt.h>

#include <linux/gpio.h>





#include <asm/mach-types.h>

#include <asm/mach-types.h>

#include <asm/mach/arch.h>

#include <asm/mach/arch.h>

arch/arm/mach-mmp/pxa168.c

+0 −1
Original line number Original line Diff line number Diff line
@@ -24,7 +24,6 @@ 
#include <mach/dma.h>

#include <mach/dma.h>

#include <mach/devices.h>

#include <mach/devices.h>

#include <mach/mfp.h>

#include <mach/mfp.h>

#include <linux/platform_device.h>

#include <linux/dma-mapping.h>

#include <linux/dma-mapping.h>

#include <mach/pxa168.h>

#include <mach/pxa168.h>