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Commit 8bc0ccf6 authored by Damien Lespiau's avatar Damien Lespiau Committed by Daniel Vetter
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drm/i915/skl: Implement WaDisableLSQCROPERFforOCL 



Signed-off-by: default avatarDamien Lespiau <damien.lespiau@intel.com>
Reviewed-by: default avatarNick Hoath <nicholas.hoath@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 9370cd98

drivers/gpu/drm/i915/i915_drv.h

+1 −0
Original line number Diff line number Diff line
@@ -2396,6 +2396,7 @@ struct drm_i915_cmd_table { 
#define SKL_REVID_B0		(0x1)

#define SKL_REVID_C0		(0x2)

#define SKL_REVID_D0		(0x3)

#define SKL_REVID_E0		(0x4)



/*

 * The genX designation typically refers to the render engine, so render

drivers/gpu/drm/i915/i915_reg.h

+3 −0
Original line number Diff line number Diff line
@@ -5259,6 +5259,9 @@ enum skl_disp_power_wells { 
#define GEN7_L3SQCREG4				0xb034

#define  L3SQ_URB_READ_CAM_MATCH_DISABLE	(1<<27)



#define GEN8_L3SQCREG4				0xb118

#define  GEN8_LQSC_RO_PERF_DIS			(1<<27)



/* GEN8 chicken */

#define HDC_CHICKEN0				0x7300

#define  HDC_FENCE_DEST_SLM_DISABLE		(1<<14)

drivers/gpu/drm/i915/intel_pm.c

+5 −0
Original line number Diff line number Diff line
@@ -65,6 +65,11 @@ static void skl_init_clock_gating(struct drm_device *dev) 
			   GEN8_GAPSUNIT_CLOCK_GATE_DISABLE |

			   GEN8_SDEUNIT_CLOCK_GATE_DISABLE);

	}



	if (INTEL_REVID(dev) <= SKL_REVID_E0)

		/* WaDisableLSQCROPERFforOCL:skl */

		I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |

			   GEN8_LQSC_RO_PERF_DIS);

}



static void i915_pineview_get_mem_freq(struct drm_device *dev)