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Commit 86ee27b5 authored by Yetunde Adebisi's avatar Yetunde Adebisi Committed by Jani Nikula
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drm/i915: Read eDP Display control capability registers 



Add new edp_dpcd variable to intel_dp.
Read and save eDP Display control capability registers to edp_dpcd.

Signed-off-by: default avatarYetunde Adebisi <yetundex.adebisi@intel.com>
Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1459865452-9138-3-git-send-email-yetundex.adebisi@intel.com
parent 4e382db3

drivers/gpu/drm/i915/intel_dp.c

+10 −5
Original line number Diff line number Diff line
@@ -3747,7 +3747,6 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp) 
	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

	struct drm_device *dev = dig_port->base.base.dev;

	struct drm_i915_private *dev_priv = dev->dev_private;

	uint8_t rev;



	if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,

				    sizeof(intel_dp->dpcd)) < 0)
@@ -3804,6 +3803,15 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp) 
			DRM_DEBUG_KMS("PSR2 %s on sink",

				dev_priv->psr.psr2_support ? "supported" : "not supported");

		}



		/* Read the eDP Display control capabilities registers */

		memset(intel_dp->edp_dpcd, 0, sizeof(intel_dp->edp_dpcd));

		if ((intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&

				(intel_dp_dpcd_read_wake(&intel_dp->aux, DP_EDP_DPCD_REV,

						intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==

								sizeof(intel_dp->edp_dpcd)))

			DRM_DEBUG_KMS("EDP DPCD : %*ph\n", (int) sizeof(intel_dp->edp_dpcd),

					intel_dp->edp_dpcd);

	}



	DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink %s\n",
@@ -3811,10 +3819,7 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp) 
		      yesno(drm_dp_tps3_supported(intel_dp->dpcd)));



	/* Intermediate frequency support */

	if (is_edp(intel_dp) &&

	    (intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] &	DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&

	    (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_EDP_DPCD_REV, &rev, 1) == 1) &&

	    (rev >= 0x03)) { /* eDp v1.4 or higher */

	if (is_edp(intel_dp) && (intel_dp->edp_dpcd[0] >= 0x03)) { /* eDp v1.4 or higher */

		__le16 sink_rates[DP_MAX_SUPPORTED_RATES];

		int i;

drivers/gpu/drm/i915/intel_drv.h

+1 −0
Original line number Diff line number Diff line
@@ -810,6 +810,7 @@ struct intel_dp { 
	uint8_t dpcd[DP_RECEIVER_CAP_SIZE];

	uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];

	uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];

	uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];

	/* sink rates as reported by DP_SUPPORTED_LINK_RATES */

	uint8_t num_sink_rates;

	int sink_rates[DP_MAX_SUPPORTED_RATES];