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Commit 85540480 authored by Zhenyu Wang's avatar Zhenyu Wang Committed by Chris Wilson
Browse files

intel_agp,i915: Add more sandybridge graphics device ids



New pci ids for GT2 and GT2+ on desktop and mobile sandybridge,
and graphics device ids for server sandybridge. Also rename original
ids string to reflect GT1 version.

Signed-off-by: default avatarZhenyu Wang <zhenyuw@linux.intel.com>
Cc: stable@kernel.org
Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
parent a69ffdbf
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+12 −3
Original line number Diff line number Diff line
@@ -816,11 +816,19 @@ static const struct intel_driver_description {
	    "HD Graphics", NULL, &intel_i965_driver },
	{ PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB, PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG,
	    "HD Graphics", NULL, &intel_i965_driver },
	{ PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB, PCI_DEVICE_ID_INTEL_SANDYBRIDGE_IG,
	{ PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB, PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT1_IG,
	    "Sandybridge", NULL, &intel_gen6_driver },
	{ PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB, PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_IG,
	{ PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB, PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_IG,
	    "Sandybridge", NULL, &intel_gen6_driver },
	{ PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB, PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_D0_IG,
	{ PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB, PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_PLUS_IG,
	    "Sandybridge", NULL, &intel_gen6_driver },
	{ PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB, PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT1_IG,
	    "Sandybridge", NULL, &intel_gen6_driver },
	{ PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB, PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_IG,
	    "Sandybridge", NULL, &intel_gen6_driver },
	{ PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB, PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_PLUS_IG,
	    "Sandybridge", NULL, &intel_gen6_driver },
	{ PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_HB, PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_IG,
	    "Sandybridge", NULL, &intel_gen6_driver },
	{ 0, 0, NULL, NULL, NULL }
};
@@ -1045,6 +1053,7 @@ static struct pci_device_id agp_intel_pci_table[] = {
	ID(PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB),
	ID(PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB),
	ID(PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB),
	ID(PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_HB),
	{ }
};

+12 −6
Original line number Diff line number Diff line
@@ -202,11 +202,16 @@
#define PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB	    0x0062
#define PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB    0x006a
#define PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG	    0x0046
#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB  0x0100
#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_IG  0x0102
#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB  0x0104
#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_IG  0x0106
#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_D0_IG  0x0126
#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB		0x0100  /* Desktop */
#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT1_IG		0x0102
#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_IG		0x0112
#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_PLUS_IG	0x0122
#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB		0x0104  /* Mobile */
#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT1_IG	0x0106
#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_IG	0x0116
#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_PLUS_IG	0x0126
#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_HB		0x0108  /* Server */
#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_IG		0x010A

/* cover 915 and 945 variants */
#define IS_I915 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_E7221_HB || \
@@ -233,7 +238,8 @@
		agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_PINEVIEW_HB)

#define IS_SNB (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB || \
		agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB)
		agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB || \
		agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_HB)

#define IS_G4X (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_EAGLELAKE_HB || \
		agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q45_HB || \
+2 −2
Original line number Diff line number Diff line
@@ -618,8 +618,7 @@ static void intel_i830_init_gtt_entries(void)
			gtt_entries = 0;
			break;
		}
	} else if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB ||
		   agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB) {
	} else if (IS_SNB) {
		/*
		 * SandyBridge has new memory control reg at 0x50.w
		 */
@@ -1389,6 +1388,7 @@ static void intel_i965_get_gtt_range(int *gtt_offset, int *gtt_size)
		break;
	case PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB:
	case PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB:
	case PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_HB:
		*gtt_offset = MB(2);

		pci_read_config_word(intel_private.pcidev, SNB_GMCH_CTRL, &snb_gmch_ctl);
+4 −0
Original line number Diff line number Diff line
@@ -175,8 +175,12 @@ static const struct pci_device_id pciidlist[] = { /* aka */
	INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info),
	INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info),
	INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info),
	INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info),
	INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info),
	INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info),
	INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info),
	INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info),
	INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info),
	{0, 0, 0}
};