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Commit a69ffdbf authored by Zhenyu Wang's avatar Zhenyu Wang Committed by Chris Wilson
Browse files

drm/i915: Enable MI_FLUSH on Sandybridge 



MI_FLUSH is being deprecated, but still available on Sandybridge.
Make sure it's enabled as userspace still uses MI_FLUSH.

Signed-off-by: default avatarZhenyu Wang <zhenyuw@linux.intel.com>
Cc: stable@kernel.org
Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
parent f8f235e5

drivers/gpu/drm/i915/i915_reg.h

+1 −0
Original line number Diff line number Diff line
@@ -319,6 +319,7 @@ 


#define MI_MODE		0x0209c

# define VS_TIMER_DISPATCH				(1 << 6)

# define MI_FLUSH_ENABLE				(1 << 11)



#define SCPD0		0x0209c /* 915+ only */

#define IER		0x020a0

drivers/gpu/drm/i915/intel_ringbuffer.c

+6 −2
Original line number Diff line number Diff line
@@ -220,9 +220,13 @@ static int init_render_ring(struct drm_device *dev, 
{

	drm_i915_private_t *dev_priv = dev->dev_private;

	int ret = init_ring_common(dev, ring);

	int mode;



	if (IS_I9XX(dev) && !IS_GEN3(dev)) {

		I915_WRITE(MI_MODE,

				(VS_TIMER_DISPATCH) << 16 | VS_TIMER_DISPATCH);

		mode = VS_TIMER_DISPATCH << 16 | VS_TIMER_DISPATCH;

		if (IS_GEN6(dev))

			mode |= MI_FLUSH_ENABLE << 16 | MI_FLUSH_ENABLE;

		I915_WRITE(MI_MODE, mode);

	}

	return ret;

}